I have a gurobi optimization problem, now I set the objective using quicksum(quicksum ...) but it takes a long time for the objective to be added, I want to add the objective one by one to check where it might go wrong, how should I do it?
I have no idea yet. I am considering using a bunch of for loops.
Related
As title indicates, the or tools uses overall route driving time(or distance) as objective function and searches for a solution combination that minimizes the sum of driving times (or distances) for all routes using below line of code:
search_parameters.first_solution_strategy = (
routing_enums_pb2.FirstSolutionStrategy.PATH_CHEAPEST_ARC)
What if I want to have a custom objective function, like I want to minimize the number of stops that I am unable to reach within time window, or minimize the number of stops that are dropped from the solution. etc?
I was wondering if there were a way to compute the size of a reg in Verilog. I researched it quite a bit, and found $size(a), but it's only in SystemVerilog, and it won't work in my verilog program.
Does anyone know an alternative for this??
I also wanted to ask as a side note; I'm having some trouble with my test bench in the sense that when I update a value in the file, that change is not taken in consideration when I simulate. I've been told I might have been using an old test bench but the one I am continuously simulating is the only one available in this project.
EDIT:
To give you an idea of what's the problem: in my code there is a "start" signal and when it is set to 1, the operation starts. Otherwise, it stays idle. I began writing the test bench with start=0, tested it and simulated it, then edited the test bench by setting start to 1. But when I simulate it, the start signal remains 0 in the waveform. I tried to check whether I was using another test bench, but it is the only test bench I am using in this project.
Given that I was on a deadline, I worked on the code so that it would adapt to the "frozen" test bench. I am getting now all the results I want, but I wanted to test some other features of my code, so I created a new project and copy pasted the code in new files (including the same test bench). But when I ran a simulation, the waveform displayed wrong results (even though I was using the exact same code in all modules and test bench). Any idea why?
Any help would be appreciated :)
There is a standardised way to do this, but it requires you to use the VPI, which I don't think you get on Modelsim's student edition. In short, you have to write C code, and dynamically link it to the simulator. In the C code, you can get object properties using routines such as vpi_get. Useful properites might be vpiSize, which is what you want, vpiLeftRange, vpiRightRange, and so on.
Having said all that, Verilog is essentially a static language, and objects have to be declared with a static width using constant expressions. Having a run-time method to determine an object's size is therefore of pretty limited value (since you should already know it), and may not solve whatever problem you actually have. Your question would make more sense for VHDL (and SystemVerilog?), which are much more dynamic.
Note on Icarus: the developers have pushed lots of SystemVerilog stuff back into the main language. If you take advantge of this you may find that your code is not portable.
Second part of your question: you need to be specific on what your problem actually is.
I would like to partially solve a MIP, clone the problem and have that copy of the problem continue optimization but with a different strategy (node selection rule, variable selection rule, etc), and keeping the current branch-and-bound tree. I know that this can't be done with either CPLEX or Gurobi, since they would start optimization from scratch in the copy.
Is there any way of doing this with SCIP?
I would really appreciate any help.
Best,
Rodolfo
If you don't insist on having a copy/clone, you always have the possibility to code your stopping criterion in terms of an event handler. I am sure you know our How to on adding event handlers.
There is also an event handler in the scip source code, the so-called soft time limit event handler src/scip/event_softtimelimit.c. There you can find sample code that changes the time limit after the first solution has been found. Parameters can be fed one by one by using the SCIPchg{Real,Bool,Int,Longint,Char,String}Param() methods in the code, or passed as a settings file, which might be easier if you want to change lots of parameters without adapting the code each time.
It is good practice to use settings files saved via the set diffsave command, which saves only the nondefault-settings. Otherwise, using a complete settings file, you might run into troubles because a time limit or memory limit gets changed without control.
A copy that includes data structures such as the tree used during the branch-and-bound solving process is currently not possible. The copy-mechanism of SCIP only allows to copy the problem as a whole and adjust the formulation by changing variable domains and/or objective coefficients.
This may seem strange, so I will try to explain it as best I can:
I want to write an application for OS X that will accept some code as an input and will produce a visual output. The input will be in Objective C and the output will be the output that this code describes.
The output may be text or graphics based, it doesn't matter. What matters is that I don't know how can I make this input be handled as Objective C code and be executed by the system as such. I have a big experience with Objective C, but I hadn't had the chance to get involved with something like this.
Can anyone point me in the right direction?
So if I understand correctly, you want to:
Take Objective-C input
Parse it
And show its structure to the user in a visually digestible form.
Now the hard part is parsing it - for that you'll need a compiler front-end, possibly LLVM-clang. When you have an abstract syntax tree of the code, you can walk that tree and easily construct some graphics or structured, human-readable text to describe what the code does.
Edit: so you want to actually compile and execute that code. Then you have to go one step further and compile the code then run it.
I am trying to convert previously objective C code which is without ARC into ARC. I am fallowing the procedure like in Xcode: File > Edit > Refactor > Convert to ARC.
But I am not able to convert it, because it's generating lots of errors. I searched about this; I am trying to change the build settings in Xcode Target.
The Convert to ARC tool is not a magic bullet that makes your project suddenly ARC ready. What the tool is does is remove all of your calls to things like release & retain, it can also take care of switching some autorelease pools to the new #auto release {} style.
Before it does any of this it runs a pre-flight script to look for stuff that is too complicated for it to figure out and flags them as errors so you can go through each one and make the correct fix.
You need to step through each one of those 84 issues and figure out the solution to each one. Most likely there are half a dozen or so kinds of errors that are in multiple places but each occurrence may have a slightly different solution. Xcode may suggest a few possible fixes for some of the errors (any of the errors that show a stop sign with a white square in it have possible fixes, Xcode just doesn't know which one to use so you need to pick). Some of the issues will be easily solvable with a little help from Google. There will also likely be more errors than that in the end (I converted one project over that each time I fixed errors and tried to convert it reported more).
For the errors that you can't figure out after doing some research you should post questions about here, make sure to be specific as there are many possible things that could cause issues when converting to ARC.