Why does the order of the lines of code not matter in Hardware Description Language? - hdl

Question

Per the nand2tetris course material, "Since the language is designed to describe connections rather than processes, the order of the PARTS statements is insignificant: as long as the chip-parts are connected correctly, the chip will function as stated."
How does the sequence of the code below not matter though given that the carry bits are calculated using the carry bits of previous bit calculations?
/**
* Adds two 16-bit values.
* The most significant carry bit is ignored.
*/
CHIP Add16 {
IN a[16], b[16];
OUT out[16];
PARTS:
HalfAdder(a=a[0], b=b[0], carry=carry0, sum=out[0]);
FullAdder(a=a[1], b=b[1], c=carry0, carry=carry1, sum=out[1]);
FullAdder(a=a[2], b=b[2], c=carry1, carry=carry2, sum=out[2]);
FullAdder(a=a[3], b=b[3], c=carry2, carry=carry3, sum=out[3]);
FullAdder(a=a[4], b=b[4], c=carry3, carry=carry4, sum=out[4]);
FullAdder(a=a[5], b=b[5], c=carry4, carry=carry5, sum=out[5]);
FullAdder(a=a[6], b=b[6], c=carry5, carry=carry6, sum=out[6]);
FullAdder(a=a[7], b=b[7], c=carry6, carry=carry7, sum=out[7]);
FullAdder(a=a[8], b=b[8], c=carry7, carry=carry8, sum=out[8]);
FullAdder(a=a[9], b=b[9], c=carry8, carry=carry9, sum=out[9]);
FullAdder(a=a[10], b=b[10], c=carry9, carry=carry10, sum=out[10]);
FullAdder(a=a[11], b=b[11], c=carry10, carry=carry11, sum=out[11]);
FullAdder(a=a[12], b=b[12], c=carry11, carry=carry12, sum=out[12]);
FullAdder(a=a[13], b=b[13], c=carry12, carry=carry13, sum=out[13]);
FullAdder(a=a[14], b=b[14], c=carry13, carry=carry14, sum=out[14]);
FullAdder(a=a[15], b=b[15], c=carry14, carry=carry15, sum=out[15]);

Answer 1

Because all the calculations are being computed concurrently. In an hdl each instance of a block/entity/module create an instance of all the behaviors inside. You didn't specify which one you're using, but almost all behave the same.