I am working on MM32Spin05 MCU. After power on, all 6 flags in the RCC(Reset and Clock Control) register are getting set.
After a reset, the default value of this register should be 0X XC000000.
But I am observing it as 0X FC000000.
I am not doing anything with respect to the watchdog timers, or the low power module or the s/w reset.
I have a requirement, that, if a software reset is done, a certain page in the flash memory is to be cleared. But on boot up, the flag is set for reasons unknown to me and hence, the flash memory page is getting cleared.
I am actually doing a Power Reset. I am turning off and then turning on the power supply to the MCU. On boot-up, the Software Reset flag is set and hence, according to my code, it is triggering the flash memory page erase. The Flash memory page should be erased ONLY on a software reset, not a power reset. Immediately after the MCU boots up, I print the RCC_CSR Register value, and see that all 6 flags are set.
LPWRRSTF: Low power reset flag
WDGRSTF: Window watchdog reset flag
IWDGRSTF: Independent watchdog reset flag
SFTRSTF: Software reset flag
PORRSTF: POR/PDR reset flag
PINRSTF: PIN reset flag
I am confused, as to why, a power reset is causing the software reset flag to set?
I am stuck on this for more than a week and am fully clueless about it. Any help or suggestions would be highly welcome.
Thanks in Advance
As the manual says, the top 4 bits are "don't care" on power-on (or pin) reset, and they can have any value.
Only if none of PORRSTF and PINRSTF are set, the other bits are relevant.
Even then you need to read the manual carefully to understand the conditions of these bits. There might be more to do than a simple single-bit check.
Related
Board: MSP-EXP432P401R
MCU: MSP432P401R
How do I count the number of times the watchdog timer has been reset?
Can anyone help me in this.
Write code to detect that a watchdog reset has occurred. The microcontroller may have a register flag that indicates the reason for the previous reset (e.g., hard, soft, brown-out, watchdog, etc.). Look for this register flag in the reset or power control registers in your microcontroller's reference manual. Read this register flag during system initialization to detect that a watchdog reset occurred. Or alternately, enable the watchdog reset interrupt handler to detect that a watchdog reset is occurring.
When a watchdog reset is detected, increment a counter variable and save the counter value to nonvolatile memory. Read/restore the watchdog counter value from nonvolatile memory during system initialization or before incrementing the count. Saving the count value in nonvolatile memory allows the count value to be remembered through a power loss.
TI don't make it easy to find the documentation! The MSP432FR401 datasheet has a broken link to the reference manual. I can only find copies at various non-TI sites such as this. YMMV.
Section 3.3.2 and 3.3.5 describe the hard and soft reset status registers respectively. The one you need depends on how you have configured the watchdog timer (section 4.11.3).
The reset sources are device specific and not explicitly stated in the general user manual. It refers you to the datasheet. Unfortunately as far as I can find, the promised information is not there either! I suggest that you experiment and read the register on start-up following a reset and determine which bit is unique to a watchdog reset rather than say a power-on reset. (To be honest however I'd also suggest not using a part so poorly documented and supported).
If you can determine which RSTCTL_HARDRESET_STAT/RSTCTL_SOFTRESET_STAT bit relates specifically to a watchdog reset, you can test it on start-up and increment your counter. Neither your board or MCU have any convenient non-volatile storage for such a counter. If you only need to count watchdog resets whilst continuously powered, you can keep the counter in a reserved location in SRAM (a specific address not initialised on start-up and not available to the linker to locate data objects), but if you want a "lifetime" count, then you may need to dedicate an entire 4K flash sector to the counter (and deal with the flash endurance issue - that probably warrants a new question if it is relevant).
I have a bootloader and a firmware where the initial jump from bootloader to firmware works like a charme but when I have the scenario jumping back from application, make some stuff and jump back to my application. There I got some curious problem which ends in a hard fault. This problem comes up if I will activate the interrupts via __enable_interrupts() from IAR.
What are the right register to clear and reset all?
I have set the MSP and the PC to the beginning of the application/bootloader.
It is neccessary that I don't use NVIC_Systemreset for that purpose.
Hope anyone can help me with that question?
There is an ST application note about bootloader.
In addition to patterns described above, user can execute bootloader
by performing a jump to system memory from user code. Before jumping
to bootloader user must:
Disable all peripheral clocks
Disable used PLL
Disable interrupts
Clear pending interrupts
This is why when you activate interrupts the bootloader crashes.
EDIT
To address #Clifford thoughts STM32 system bootloader exits with jump to master defined address with go command. This address should be reset vector not main so that heap, stack and FW will be correctly initialized. After that you can either do system_reset to be in a known HW state or you must fully configure the peripherals you use in application because they are not set bat to reset state after bootloader used them.
Note: If you choose to execute the Go command, the peripheral
registers used by the bootloader are not initialized to their default
reset values before jumping to the user application. They should be
reconfigured in the user application if they are used. So, if the IWDG
is being used in the application, the IWDG prescaler value has to be
adapted to meet the requirements of the application (since the
prescaler was set to its maximum value). For some products, not all
reset values are set. For more information please refer to the known
limitations detailed for each product’s bootloader versions.
sorry for late response.
After some more investigations I have found the problems.
For more clarifications about what I have done, here are some points which were also mentioned by your comments.
Disabled all Peripherals
Disbaled PLL
Disabled all interrupts
Clear alle pending interrupts
What I unfortunately forgot to mention that we use embOS.
And this was the problem here. There is the CORE registers http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0552a/CHDBIBGJ.html
In the CONTROL Register there was a bit set: SPSEL
If this bit is set to "1" then embOS got problems with normal operation.
The solution for this is simple:
__set_CONTROL(0x0);
When this is called the jumping from embOS to Bootloader and back to embOS works perfectly.
how can I determine whether the power up is because power cut Or reset
I am working on STM32L152ZE
Regards,
Look up the datasheet for your processor.
Find the system status registers. There will be one that signifies the reason for boot up (for example, in a PIC, there is one that has bits indicating whether the boot was due to a watchdog timer, reset line, etc.)
Interrogate this register to find your answer.
The STM32L100/151/152/162 User Manual section section 6.3.14 describes the RCC_CSR register which has bit flags for all reset causes including Power On/Power Down Reset.
In my opinion:
soft reset: boots from the reset vector.
hard reset: pull the electrical level of the cpu.
A hard reset certainly means that the whole CPU chip and all its peripherals are reset. The causes for this could be many: reset pin pulled externally, clock failures, on-chip low-voltage detection, watchdog, illegal instruction traps etc etc.
A soft reset probably means a "dirty" branch to back to the reset vector, where the reset vector restores all CPU core registers including the stack. I would say that this is very questionable practice and I'm not sure what good it would do. The main problem is that all MCU peripheral hardware registers will -not- get reset to default when you do this. It is almost impossible not to make any assumptions about the reset state of all such registers, especially since the average MCU comes with 1000+ of them nowadays. So with this soft & dirty reset, you will most likely end up a behaviour like this:
subtle intermittent bugs <= my program <= complete haywire
More far-fetched, a soft reset could mean a reset caused by software. In that case it could be writing the wrong value to the watchdog register to enforce a reset, or failing to refresh the watchdog. Or it could be the execution of an illegal instruction. These will most likely cause a complete reset of the whole chip.
This can very from chip to chip I assume. The hard reset is probably agreed to be the reset line on the device (pin, ball, etc) when pulled in a certain direction puts some or all of the chip in reset. Soft reset, could be as simple as a branch to zero or branch to the reset vector, or it could be a register you write or a bit in a register that causes a hard reset, or perhaps something close to a hard reset, imagine a layer inside the chip, the hard reset hits the outer layer, the soft reset hits some inside layer possibly not the whole chip. for example you maybe you dont want to fall off the pcie bus so you leave that alone. Normally jtag (or some portion of it) for example shouldnt be touched by either reset. When software pulls a reset line it kills itself, who is going to release that reset? Something in hardware, many ways to solve this, but if solved with something that has a digital component to it that digital section shouldnt get hit with the reset the software has hit or you again get stuck not being able to release it.
On an Intel platform, a soft reset (writing 0x4 to port 0xcf9) is a warm CPU reset, i.e. a reset while the CPU is running. A warm reset (writing 0x6 to port 0xcf9) is a host reset without a power cycle, and a hard reset (writing 0xe to port 0xcf9) is a host reset with a power cycle. A global reset is a reset of the Intel ME combined with a host reset.
A cold CPU reset is the assertion of RESET# while power is initially being supplied to the CPU. A warm CPU reset is when INIT# or RESET# occurs while V_cc and CLK remain in specified operating limits. If you just INIT# then it just flushes the BTB and TLBs and only initialises integer registers and goes to the restart MSROM routine (no longer just 0xFFFFFFF0 on UEFI systems). If you RESET# then it flushes the caches as well and initialises FP registers and not just the integer registers. This is the initial state of the registers, I think before the microcode begins. If you assert both INIT# and RESET# together then it does a BIST as well. I think in this case it reperforms the BSP selection process aka. the MP Initialisation protocol, because a BIPI is sent to all-including-self after the BIST completes, and I think it also performs BSP selection when there is no BIST i.e. just a RESET# when warm/cold (this talks about sending a BIPI after an optional BIST on reset). On modern Intel CPUs, I think RESET# is one per socket and resets all cores, and is tied to the PCH PLTRST#, whereas INIT is sent by the PCH over DMI in a PCIe VLW transaction, and is distributed on a core by core basis to the specified cores configured in a CPU register like QPIPNCB.
A warm reset is an assertion of PLTRST# by the PCH which goes to many components, and the system stays in S0. On a hard reset, the system cycles through SLP_S0# to SLP_S5# and then cycles up through SLP_S5# to SLP_S0# to end up in S0 C0 (when PLTRST# is eventually deasserted), this will result in DRAM being reset, which PLTRST# on its own doesn't do. SLP_S0 - S5# high means the CPU is in S0 C0. SLP_S0# low means it is in S0 Cx, SLP_S0# and SLP_S3# low means it is in S3, SLP_S0# and SLP_S3# and SLP_S4# low means it is in S4 and so on.
A cold reset I think is when the system boots from G3 and needs to go through PCH_RTCRST# and EC_RSMRST# before returning to the state it was in before the G3, which could be DeepSx, S5 or S4. But you will see people call the hard reset a cold reset, and the cold reset a cold boot. I would probably use the terms hard reset and cold boot. A warm boot would be a S3 resume and a cold boot would be booting from S4/S5/G3, maybe you could all S4/S5 a hard boot and G3 a cold boot.
It can mean whatever the system designer wants it to mean. There is no generic definition. For example, the content of RAM may be maintained through a soft reset, but not through a hard reset, or it may simply be the difference between an external hardware reset signal and a software RESET instruction.
I need to implement the following feature for my device running embedde linux on a 200mhz MIPS cpu:
1) if a reset button is pressed and held for less then a second - proceed with reboot
2) if a reset button is pressed and held for at least 3 sec. - restore the system's configuration with default values from NVRAM and then reboot.
I'm thinking of two ways:
1) a daemon that constantly polls the button's state with proper timings via GPIO ioctls
(likely too big overhead, lots of context switching ?)
2) simple char driver polling the button, measuring timings and reporting the state, for example, via /proc to user space where daemon or a shell script can check and do what's required.
And for both cases I have no idea how to measure the time :(
What would you suggest/recommend?
You have to implement those in hardware. The purpose of the "restore defaults from NVRAM" is to restore a so-called "bricked" device.
For example, what if an NVRAM seting is modified (cosmic ray?) such that the device cannot boot? In that case, your proposed button-polling daemon will never execute.
For the one-second held reboot, use an RC (resistor + capacitor) circuit to "debounce" the button press. Select an RC time constant which is appropriate for the one second delay. Use a comparator watching the RC voltage to signal the RESET pin on the MIPS cpu.
For the three-second press functionality (restore NVRAM defaults), you have to do something more complicated, probably.
One possibility is to put a tiny PIC microcontroller into the reset circuit, but only use a microcontroller with fuse (non-erasable) ROM, not NVRAM.
An easier possibility is to have a ROM containing defaults on the same circuit and bus as the NVRAM. A J/K flip-flop latch can become part of your reset circuitry. You'll also need a three-second-tuned RC circuit and comparator. On sub-three-second presses, the flip-flop should latch a 0 output and on three-second-plus presses, the 2nd RC circuit should trigger the comparator after 3 seconds and present a 1 to the J/K latch, which will toggle its output.
The flip-flop output Q will store the single bit telling your circuit whether this reset cycle was subsequent to a three-second push. If so, that output Q is driving the chip select to the NVRAM and Q* is driving the chip select to ROM. (I assume chip select is negative logic on both NVRAM and ROM chips.)
Then when your CPU boots, it will fetch the settings from either the NVRAM or the ROM, depending on the chip select line.
Your boot code can detect that it booted with ROM chip select, and can later reset the J/K flip-flop with a GPIO line. Then the CPU will be able to write good values back into the NVRAM. That unbricks the device, hopefully.
You want to use ROM that is not erasable or reusable. That kind of ROM is the most resistant to static electricity, power supply trouble, and radiation. Radiation is much more present than we generally realize, and the amount of cosmic ray flux is multiplied by taking a device onboard an airliner, for example.
I am not familiar with the MIPS processor and the GPIO/interrupt capabilities of the pin that you could be using but a possible methodology could be as follows.
Configure the input pin as an interrupt input.
When the interrupt fires disable the interrupt and start a short 100ms-ish timer
When the timer triggers check that the button is still pressed (for debounce). If it is not then re-enable the GPIO interrupt and restart, otherwise set the timer to re-trigger after the 3 second timeout.
When the timer triggers this time then if the button is not pressed then do your reboot otherwise reset the system configuration and reboot.
If the pin cannot provide an interrupt then step 1 will be a polling task to look at the input.
The time between the reset button being pressed and the full reset process being run will always be 3 seconds from a debounced button press. In a reset situation this may not be important particularly if as part of step 3 you make it apparent to the user that a reset sequence has started - blank the display for example.
If you want to do this in software, you need to put this in kernel (interrupt) code, rather than in a shell script or daemon. The better approach would be to put this in hardware.
In my experience, the likely reason for resetting the device will be bad user code which has locked or bricked the processor. If the issue is a corruption of memory due to RF energy or something of that nature, you may require hardware or an external (hardened) processor to reflash the device and fix the problem.
In the bad-user-code case, processor interrupts and kernel code should continue to run, while user code may be completely stalled. If you can poll the pin from an interrupt, you stand a much better chance of actually getting the reset you expect. Also, this enables you to do event-driven programming, rather than constantly polling the pin.
One other approach (not to the specs you listed, but a popular method for achieving the same goal) would be to have the startup routines check a GPIO line, and hold a button down when you want to re-initialize the device. On most embedded Linux devices which I've seen, the "Reset" button is wired to a dedicated reset pin on the microcontroller, and not to a GPIO pin. You may have to go with this route, unless you want to start cutting traces.