I have a C program with a path like this :
pgrmusinglib.c
pgrmusinglib.h
main.c
libfolder
libmylibrary.dll
I am trying to compile it on windows using mingw64.
I built this Makefile
CC = gcc
CFLAGS = -O3
DEPS = pgrmusinglib.h
LDFLAGS = -L/$(LIB) -lmylibrary
LIB = libfolder
SRC=$(wildcard *.c)
OBJ = $(SRC:.c=.o)
all: pgrm
pgrm : $(OBJ)
$(CC) -o $^ $(LDFLAGS)
%.o: %.c $(DEPS)
$(CC) -c $^ $(CFLAGS)
The pgrm rule fails with error :
c:/programdata/chocolatey/lib/mingw/tools/install/mingw64/bin/../lib/gcc/x86_64-w64-mingw32/10.2.0/../../../../x86_64-w64-mingw32/bin/ld.exe:
cannot find -lmylibrary
I believe it is'nt working because of how you wrote the LDFLAGS, just a little typo I assume, you put a '/' in front of the directory name , so its looking for libfolder in your root directory. Try either removing the '/' or putting a period '.' In front of it
Related
I am kinda rookie in makefile field but trying to write makefile that would go in two modes: normal mode make outputing executable file called say bingo depending on some files and a mode make debug outputing executable file called bingo.debug that shall be compiled with debug option. I'm trying to use target variable with the following result:
PROGRAM = bingo
SUFIX = .debug
CC = gcc
CFLAGS = -Wall -O2
DEBUG = -g -D DEBUG
all: $(PROGRAM)
debug: CFLAGS += $(DEBUG)
debug: PROGRAM += $(SUFIX)
debug: all
file1.o: file1.c file1.h
$(CC) -c $(CFLAGS) -o $# $<
file2.o: file2.c file2.h
$(CC) -c $(CFLAGS) -o $# $<
$(PROGRAM).o: $(PROGRAM).c
$(CC) -c $(CFLAGS) -o $# $<
$(PROGRAM): file1.o file2.o ($PROGRAM).o
$(CC) -o $# $^
.PHONY: all clean
clean:
rm -rf $(PROGRAM) *.o
It looks like make debug correctly compiles the file with debug flags but it does not change the file name (i.e. both modes outputs the same bingo file). Any help much appriciated!
You cannot use target-specific variables in targets. The documentation is very clear that they are available only in recipes.
In general it's problematic to do things this way, because make has no idea which objects were built with debug and which weren't. If you forget to do a complete clean and/or run make the wrong way then you'll get a mix of different object files: some compiled with debug and some not.
Instead, you should put your debug object files in a different directory from your non-debug object files so you don't have to worry about that.
The challenge is to create a makefile which takes a list of modules and does not require me to sort out precendence. For example, the modules are
mod allocations.f08 mod precision definitions.f08 mod unit values.f08
mod blocks.f08 mod shared.f08 mod parameters.f08
mod timers.f08
The main program is characterize.f08. The error message is
Fatal Error: Can't open module file ‘mprecisiondefinitions.mod’ for reading at (1): No such file or directory
The first statement in the main program is use mPrecisionDefinitions, the module defined in mod precision definitions.f08.
The following makefile, based upon Creating a FORTRAN makefile, is:
# compiler
FC := /usr/local/bin/gfortran
# compile flags
FCFLAGS = -g -c -Wall -Wextra -Wconversion -Og -pedantic -fcheck=bounds -fmax-errors=5
# link flags
FLFLAGS =
# source files and objects
SRCS = $(patsubst %.f08, %.o, $(wildcard *.f08))
# program name
PROGRAM = a.out
all: $(PROGRAM)
$(PROGRAM): $(SRCS)
$(FC) $(FLFLAGS) -o $# $^
%.mod: %.f08
$(FC) $(FCFLAGS) -o $# $<
%.o: %.f08
$(FC) $(FCFLAGS) -o $# $<
clean:
rm -f *.o *.mod
For starters, I recommend to replace all spaces in your file names with underscores or something similar.
Spaces are almost universally used as separators, and any program that is started with something like
gfortran -c -o mod precision definitions.o mod precision definitions.f08
would interpret this line as 'create an object file called mod from the source files precision, definitions.o, mod, precision, and definitions.f08. And while there are ways to do it, with increasing automation, you have to jump more and more hoops.
In contrast, this works well:
gfortran -c -o mod_precision_definitions.o mod_precision_definitions.f08
I would use this command to change all the spaces into underscores:
rename 's/ /_/g' *.f08
If that doesn't work, use this command:
for f in *.f08; do mv "$f" ${f// /_}; done
Next, I wouldn't worry about .mod files. They get generated together with the object files when you compile a module. So while technically some routine that uses a module requires the .mod file for that module, you might as well claim in your Makefile that it depends on the object file itself.
So with that said, here's the Makefile I would use (with some assumed inter-module dependencies added):
# Find all source files, create a list of corresponding object files
SRCS=$(wildcard *.f08)
OBJS=$(patsubst %.f08,%.o,$(SRCS))
# Ditto for mods (They will be in both lists)
MODS=$(wildcard mod*.f08)
MOD_OBJS=$(patsubst %.f08,%.o,$(MODS))
# Compiler/Linker settings
FC = gfortran
FLFLAGS = -g
FCFLAGS = -g -c -Wall -Wextra -Wconversion -Og -pedantic -fcheck=bounds -fmax-errors=5
PROGRAM = characterize
PRG_OBJ = $(PROGRAM).o
# make without parameters will make first target found.
default : $(PROGRAM)
# Compiler steps for all objects
$(OBJS) : %.o : %.f08
$(FC) $(FCFLAGS) -o $# $<
# Linker
$(PROGRAM) : $(OBJS)
$(FC) $(FLFLAGS) -o $# $^
# If something doesn't work right, have a 'make debug' to
# show what each variable contains.
debug:
#echo "SRCS = $(SRCS)"
#echo "OBJS = $(OBJS)"
#echo "MODS = $(MODS)"
#echo "MOD_OBJS = $(MOD_OBJS)"
#echo "PROGRAM = $(PROGRAM)"
#echo "PRG_OBJ = $(PRG_OBJ)"
clean:
rm -rf $(OBJS) $(PROGRAM) $(patsubst %.o,%.mod,$(MOD_OBJS))
.PHONY: debug default clean
# Dependencies
# Main program depends on all modules
$(PRG_OBJ) : $(MOD_OBJS)
# Blocks and allocations depends on shared
mod_blocks.o mod_allocations.o : mod_shared.o
I am trying to compile on MacBook Pro Retina with CUDA Driver Version: 7.0.36 and cuda toolkit 7.0 in a nVidia GT 750 M, the following code with its makefile but it gives me this error:
nvcc fatal : redefinition of argument 'optimize'.
Despite I have been able to compile and execute other programes with nvcc, with makefiles and so, now I am not.
Also, I have not been able to find something useful about this error so I ask it here if someone knows how to solve it. I am new with CUDA so if you need more information please ask for it.
Here is my Makefile.inc:
CXX := nvcc
OPTIM := -O3
DEBUG := -g -DOLB_DEBUG
CXXFLAGS := $(OPTIM)
ARPRG := ar
LDFLAGS := -O3
PARALLEL_MODE := OFF
OMPFLAGS := -fopenmp
BUILDTYPE := precompiled
INPUTDIR := ./input
OUTPUTDIR := ./output
INCDIR := ./inc
OBJDIR := ./obj
SRCDIR := ./HeatTransfer
BINDIR := ./bin
###########################################################################
## defines shell
SHELL := /bin/sh
and the Makefile:
###########################################################################
ROOT := .
include $(ROOT)/Makefile.inc
######################################################## Operational system
OS = $(shell uname -s)
MACH = $(shell uname -m)
HOST = $(shell uname -n)
WHOAMI = $(shell whoami )
###########################################################################
HeatTransfer := \
mesh\
stack
PROGRAM := $(BINDIR)/program
###########################################################################
OBJECTS := $(foreach file, $(HeatTransfer), $(OBJDIR)/$(file).o)
###########################################################################
all : compile link
###########################################################################
compile : $(OBJECTS)
$(OBJDIR)/%.o: $(SRCDIR)/%.cu
#echo Compile $<
$(CXX) $(CXXFLAGS) -I$(INCDIR) -c $< -o $#
###########################################################################
link: $(PROGRAM)
$(PROGRAM): $(OBJECTS)
#echo Link $#
$(CXX) $(LDFLAGS) -I$(INCDIR) $(foreach file, $(HeatTransfer), $(OBJDIR)/$(file).o) $(LDFLAGS) -I$(INCDIR) -o $#
###########################################################################
clean : cleanprog cleanobj
cleanprog:
#echo Clean rubbish files
#rm -f *~ core .tmpfile $(PROGRAM)
cleanobj:
#echo Clean object files
#rm -f $(OBJECTS)
###########################################################################
###########################################################################
The complete messege when I try to compile is this:
...Heat_Transfer_CUDA$ make
Compile HeatTransfer/mesh.cu
nvcc -O3 -I./inc -c HeatTransfer/mesh.cu -o obj/mesh.o
Compile HeatTransfer/stack.cu
nvcc -O3 -I./inc -c HeatTransfer/stack.cu -o obj/stack.o
Link bin/program
nvcc -O3 -I./inc ./obj/mesh.o ./obj/stack.o -O3 -I./inc -o bin/program
nvcc fatal : redefinition of argument 'optimize'
make: *** [bin/program] Error 1
The problem is arising due to the fact that your link command is specifying the -O3 switch twice:
nvcc -O3 -I./inc ./obj/mesh.o ./obj/stack.o -O3 -I./inc -o bin/program
^^^ ^^^
And this is not allowed - it will produce that error.
The problem seems to occur due to the fact that your makefile specifies the use of LDFLAGS twice here:
$(CXX) $(LDFLAGS) -I$(INCDIR) $(foreach file, $(HeatTransfer), $(OBJDIR)/$(file).o) $(LDFLAGS) -I$(INCDIR) -o $#
which should not be necessary. Something like this instead:
$(CXX) $(LDFLAGS) -I$(INCDIR) $(foreach file, $(HeatTransfer), $(OBJDIR)/$(file).o) -o $#
should probably fix the issue.
I learnt from the GNU Make manual that the sign $^ is an automatic variable which represents the names of all the prerequisites. However I fell upon a makefile like this one:
SVR_OBJECT_FILES = server.o\
server_func.o
CLT_OBJECT_FILES = client.o
CFLAGS = -Wall -Werror -W
CC = gcc
all: client/client server/serveur
client/client: $(CLT_OBJECT_FILES)
server/serveur: $(SVR_OBJECT_FILES)
client/client server/serveur:
#mkdir -p $(dir $#)
$(CC) $(CFLAGS) $^ -o $#
%.o: %.c
$(CC) -c $<
clean:
rm -f client/client server/serveur *.o
Which works fine so my question is :
How can the command below can link the right object files while the $^ variable is refering no preprerequisites at all. (the rule has no prerequisites)
$(CC) $(CFLAGS) $^ -o $#
$^ contains all the prerequisites of the target, not just the ones that are mentioned with the rule itself. The same file can appear as a target several times in rules with no commands:
sometarget: dependency1
…
sometarget: dependency2
assemble -o $# $^
…
sometarget: dependency3
The dependencies of sometarget are dependency1, dependency2 and dependency3, and when the assemble command is invoked by make sometarget, it will receive all three as arguments.
Here, $^ will contain all $(CLT_OBJECT_FILES) or $(SRV_OBJECT_FILES) depending on which target the command is executed for.
When I run make on the following Makefile, when is the symbol table built, if it even is?
LEX = flex
YACC = yacc
CC = gcc
calcu: y.tab.o lex.yy.o
$(CC) -o calcu y.tab.o lex.yy.o -ly -lfl
y.tab.c y.tab.h: parser.y
$(YACC) -d parser.y
y.tab.o: y.tab.c parser.h
$(CC) -c y.tab.c
lex.yy.o: y.tab.h lex.yy.c
$(CC) -c lex.yy.c
lex.yy.c: calclexer.l parser.h
$(LEX) calclexer.l
clean:
rm *.o
rm *.c
rm calcu
make doesn't build symbol tables (obviously the compilers and linkers it invokes will have to do that!). I'll assume you're referring to whatever the resulting calcu binary does wrt its input, instead.
If any such thing as a "symbol table" is ever built by calcu, it will be by code you inserted into parser.y that gets moved over into yacc.tab.c; as to when, it will be during the course of a calcu run over whatever its input is -- incrementally, as each syntax production including "symbol-table building code" matches.