How to write consecutive case statements? - syntax-error

Question

I got an assignment to make a 4-bit booth multiplier with unsigned inputs in Verilog.
I've only used verilog a few times before this, so I'm not too familiar in writing case statements in it.
module booth(ina,inb,out);
input [3:0] ina, inb;
output[7:0] out;
reg[2:0] p1,p2;
reg[5:0] temp1, temp2;
assign p1={inb[2],inb[1],0};
assign p2={inb[3],inb[2],inb[1]};
always #(*)
begin
out = 8'b00000000;
case(p1)
3'b000: temp1=0;
3'b010: temp1=ina;
3'b100:temp1=-2 * ina;
3'b110:temp1= -ina;
endcase
end
begin
case(p2)
3'b000,3'b111: temp2=0;
3'b001,3'b010: temp2=ina;
3'b011:temp2=2 * ina;
3'b100:temp2=-2 * ina;
3'b101,3'b110:temp2= -ina;
endcase
temp2 = temp2<<2;
end
assign out=temp1+temp2;
endmodule
How am I supposed to write two case statements in a row?
I get a syntax error:
syntax error near text: "begin"; expecting "endmodule". Check for and fix any syntax errors that appear immediately before or at the specified keyword.

Answer 1

There are several compile errors.
Your error message probably refers to the 2 consecutive begin/end blocks after your always statement. One way to fix this is to add a 2nd always statement. It is a good idea to separate the temp1 and temp2 logic this way.
I also get an error for p1 because you make a continuous assignment to it with an assign statement. You should declare the signal as a wire, not a reg. Change:
reg [2:0] p1,p2;
to:
wire [2:0] p1,p2;
Another problem is that you make multiple assignments to the out signal. I think you probably want to remove it from the always block.
Lastly, you need to use a sized constant for 0 in the p1 statement. Change:
assign p1={inb[2],inb[1],0};
to:
assign p1={inb[2],inb[1],1'b0};
This code compiles cleanly for me:
module booth (ina, inb, out);
input [3:0] ina, inb;
output [7:0] out;
wire [2:0] p1,p2;
reg [5:0] temp1, temp2;
assign p1 = {inb[2], inb[1], 1'b0};
assign p2 = {inb[3], inb[2], inb[1]};
always #(*) begin
case (p1)
3'b000: temp1 = 0;
3'b010: temp1 = ina;
3'b100: temp1 = -2 * ina;
3'b110: temp1 = -ina;
endcase
end
always #(*) begin
case(p2)
3'b000,3'b111: temp2 = 0;
3'b001,3'b010: temp2 = ina;
3'b011: temp2 = 2 * ina;
3'b100: temp2 = -2 * ina;
3'b101,3'b110: temp2 = -ina;
endcase
temp2 = temp2<<2;
end
assign out = temp1+temp2;
endmodule