Problem with makefile after rename variable - variables

Question

after changing the name of a variable into a makefile, its behavior changed drastically. From unsuccessful compilation to successful one.
I tried everything - different names, adding various additional conditions, but all without success.
Version of make:
$make --version
GNU Make 3.82
Built for x86_64-redhat-linux-gnu
Copyright (C) 2010 Free Software Foundation, Inc.
License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
This is free software: you are free to change and redistribute it.
There is NO WARRANTY, to the extent permitted by law.
This is a source code file
int main(int argc, char *argv[])
{
return 0;
}
Original(desired) behavior makefile:
SHELL = /bin/sh
.SUFFIXES:
.SUFFIXES: .c .o
CC := gcc
LD := gcc
CFLAGS := -g
STRICT_CFLAGS := -Wall -Wextra -Wpedantic -Werror
INCLUDE_CFLAGS :=
ALL_CFLAGS := $(INCLUDE_CFLAGS) $(STRICT_CFLAGS) $(CFLAGS)
STRICT_LDFLAGS := -Wall -Wextra -Wpedantic -Werror
INCLUDE_LDFLAGS :=
LDFLAGS := $(STRICT_LDFLAGS) $(INCLUDE_LDFLAGS) $(CFLAGS)
SOURCES := $(wildcard *.c)
BINARIES := $(SOURCES:%.c=%)
.PHONY: all
all: $(BINARIES)
%: %.o
#echo "Checking..."
$(LD) $(LDFLAGS) -o $#
.c.o:
#echo "Creating object..."
$(CC) $(ALL_CFLAGS) -c $< -o $#
.PHONY: clean
clean:
#echo "Cleaning up..."
-rm -rvf *.o $(BINARIES)
Compile output:
$make
gcc -g -Wall -Wextra -Wpedantic -Werror -g test.c -o test
test.c: In function ‘main’:
test.c:1:14: error: unused parameter ‘argc’ [-Werror=unused-parameter]
} return 0;nt argc, char *argv[])
^
test.c:1:26: error: unused parameter ‘argv’ [-Werror=unused-parameter]
} return 0;nt argc, char *argv[])
^
cc1: all warnings being treated as errors
make: *** [test] Error 1
Makefile after renaming variable (LDFLAGS -> T_LDFLAGS) - wrong behavior:
SHELL = /bin/sh
.SUFFIXES:
.SUFFIXES: .c .o
CC := gcc
LD := gcc
CFLAGS := -g
STRICT_CFLAGS := -Wall -Wextra -Wpedantic -Werror
INCLUDE_CFLAGS :=
ALL_CFLAGS := $(INCLUDE_CFLAGS) $(STRICT_CFLAGS) $(CFLAGS)
STRICT_LDFLAGS := -Wall -Wextra -Wpedantic -Werror
INCLUDE_LDFLAGS :=
T_LDFLAGS := $(STRICT_LDFLAGS) $(INCLUDE_LDFLAGS) $(CFLAGS)
SOURCES := $(wildcard *.c)
BINARIES := $(SOURCES:%.c=%)
.PHONY: all
all: $(BINARIES)
%: %.o
#echo "Checking..."
$(LD) $(T_LDFLAGS) -o $#
.c.o:
#echo "Creating object..."
$(CC) $(ALL_CFLAGS) -c $< -o $#
.PHONY: clean
clean:
#echo "Cleaning up..."
-rm -rvf *.o $(BINARIES)
Compile output:
$make
gcc -g test.c -o test
Please someone explain to me why, after the name change, we lose flags for a strict code.
Thanks for your time!

Answer 1

Neither of your make targets are being hit. If you look at the output, you'll notice that Checking... is not printed and Creating object... is not printed. So your program is being build with the default target. This default target automatically adds $(CFLAGS) and $(LDFLAGS) to the build line. That's why things stopped working when you renamed LDFLAGS.
Also, your makefile currently is trying to create an executable for each individual .c file.
You need to change your targets as follows:
SOURCES := $(wildcard *.c)
OBJECTS := $(SOURCES:%.c=%.o)
BINARY := myprog
.PHONY: all
all: $(BINARY)
$(BINARY): $(OBJECTS)
#echo "Checking..."
$(LD) $(T_LDFLAGS) $(OBJECTS) -o $#
%.o: %.c
#echo "Creating object..."
$(CC) $(ALL_CFLAGS) -c $< -o $#
The OBJECTS variable will contain a list of .o files that correspond to each .c file. This will be the dependency list for the binary and the list of objects to link. The target for object files says to create a .o file for each .c file.