I have made a code that does arithmetic and logic operations.But when I do the compilation, the report shows that I have many syntax errors.I am a beginner in VHDL, I really do not know how to correct these mistakes,can you give me some advise?
1 library ieee;
2 use ieee.std_logic_1164.all;
3 use ieee.std_logic_unsigned.all;
4 use ieee.numeric_std.all;
5
6 package arith_operations is
7 constant size: integer :=8;
8 constant select_bits: integer :=3;
9 procedure add( x,y: in bit_vector(size-1 downto 0);
10 sum: out bit_vector(size-1 downto 0); c_out: out bit );
11 procedure sub( x,y: in bit_vector(size-1 downto 0);
12 d: out bit_vector(size-1 downto 0); c_out: out bit );
13 function inc(x: in bit_vector) return bit_vector;
14 function dec(x: in bit_vector) return bit_vector;
15 end arith_operations;
16
17 package body arith_operations is
18 procedure add( x,y: in bit_vector(size-1 downto 0); sum: out bit_vector(size-1 downto 0);
19 c_out: out bit);
20 variable s: bit_vector(size downto 0);
21 begin
22 s:= "0" & x + "0" & y;
23 sum:= s(size-1 downto 0);
24 c_out:= s(size);
25 end add;
26 procedure sub( x,y: in bit_vector(size-1 downto 0);sum: out bit_vector(size-1 downto 0;
27 c_out: out bit);
28 variable s: bit_vector(size downto 0);
29 begin
30 s:= "0" x + not("0"& y) + ((size-1 downto 0)=>"0") & "1";
31 d:= s(size-1 downto 0);
32 c_out:= s(size);
33 end sub;
34 function inc(x: in bit_vector(size-1 downto 0)) return bit_vector is
35 variable x1: bit_vector(size-1 downto 0);
36 begin
37 x1:= x + ((size-2 downto 0)=>"0") & "1";
38 return x1;
39 end inc;
40
41 function dec(x: in bit_vector(size-1 downto 0)) return bit_vector is
42 variable x1: bit_vector(size-1 downto 0);
43 begin
44 x1:= x + ((size-1 downto 0)=> "1");
45 return x1;
46 end dec;
47 end arith_operations;
48
49 use work.arith_operations.all;
50
51 entity alu is
52 generic(delay :time);
53 port( x,y: in bit_vector(size-1 downto 0);
54 function_select: in bit_vector(size-1 downto 0);
55 f: out bit_vector(size-1 downto 0);
56 end alu;
57
58 architecture behave of alu is:
59 begin
60 p0: process(x,y,function_select)
61 variable f_out: bit_vector(size-1 downto 0);
62 begin
63 case function_select is
64 when "000" => add (x, y, f_out); f<= f_out after delay;
65 when "001" => sub(x, y, f_out); f<= f_out after delay;
66 when "010" => f <= inc(x) after delay;
67 when "010" => f <= dec(x) after delay;
68 when "100" => x or y after delay;
69 when "101" => not x after delay;
70 when "110" => x and y after delay;
71 when "111" => x xor y after delay;
72 end case function_select;
73 end process p0;
74 end architecture behave;
also these are the mistakes :
Error (10500): VHDL syntax error at Alu.vhd(21) near text "begin"; expecting "end", or a declaration statement
Error (10396): VHDL syntax error at Alu.vhd(25): name used in construct must match previously specified name "arith_operations"
Error (10500): VHDL syntax error at Alu.vhd(26) near text "procedure"; expecting "entity", or "architecture", or "use", or "library", or "package", or "configuration"
Error (10500): VHDL syntax error at Alu.vhd(56) near text "end"; expecting an identifier ("end" is a reserved keyword), or "constant", or "file", or "signal", or "variable"
Error (10500): VHDL syntax error at Alu.vhd(60) near text ")"; expecting ":", or ","
Error (10500): VHDL syntax error at Alu.vhd(62) near text "begin"; expecting an identifier ("begin" is a reserved keyword), or "constant", or "file", or "signal", or "variable"
Error (10500): VHDL syntax error at Alu.vhd(64) near text ")"; expecting ":", or ","
Error (10500): VHDL syntax error at Alu.vhd(65) near text ")"; expecting ":", or ","
I tried to correct them ,but it looks like some of the errors do not make sense because I have all the punctuation marks that errors show.Also I have set the file as top-evel entity.
There were still a few syntax errors in your code. You should be able to solve them by yourself but some of the notes that I've made:
Declaring a procedure inside a package body should start with e.g. procedure add(...) is. The line should not end with a semicolor, you've done this correctly with functions.
With the expression (size-1 downto 0)=> "1" you've probably wanted to make a vector of size "size" containing only 1s? To achieve this, use an expression e.g. x1'range => '1' where x1 can be a vector variable of which size is size.
You use + operator for bit_vector type which is not defined. You probably intended to use std_logic_vector type because you imported ieee.std_logic_unsigned.all. Alternatively use numeric_bit_unsigned package.
Btw. this package is not supported so you might want to change the data type with a conversion to unsigned and use ieee.numeric_std.all package instead.
There might be errors about undeclared types etc. Check how you use the use statements.
There are other small syntax errors as well (and some logic errors, I think) but you should be able to solve them after these fixes by reading the error messages.
Related
I'm relatively new to VHDL, so I apologize before hand for the solution to this question probably appearing painstakingly obvious to most of you. In this code, I am trying to simulate a 4-bit ripple carry adder. However, when I check the syntax of the code a I run into a few errors having to do with type mismatches.
Relevant Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity toplevel is
Port ( x : in STD_LOGIC_VECTOR (3 downto 0);
y : in STD_LOGIC_VECTOR (3 downto 0);
sum : out STD_LOGIC_VECTOR (3 downto 0);
cin : in STD_LOGIC;
count : out STD_LOGIC);
end toplevel;
40: architecture Structure of toplevel is
signal c1, c2, c3 : STD_LOGIC;
component mytutorial02
Port(
x : in STD_LOGIC;
y : in STD_LOGIC;
cin : in STD_LOGIC;
sum : out STD_LOGIC;
count : out STD_LOGIC);
end component;
begin
54: Stage0: mytutorial02 port map(x=>x(0), y=>(0), cin=>cin, sum=>sum(0), count=>c1);
55: Stage1: mytutorial02 port map(x=>x(1), y=>(1), cin=>c1, sum=>sum(1), count=>c2);
56: Stage2: mytutorial02 port map(x=>x(2), y=>(2), cin=>c2, sum=>sum(2), count=>c3);
57: Stage3: mytutorial02 port map(x=>x(3), y=>(3), cin=>c3, sum=>sum(3), count=>count);
end Structure;
&
entity mytutorial02 is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
cin : in STD_LOGIC;
sum : out STD_LOGIC;
count : out STD_LOGIC);
end mytutorial02;
architecture Behavioral of mytutorial02 is
begin
sum <= (x xor y xor cin);
count <= (cin and x) or (x and y) or (cin and y);
end Behavioral;
The errors specifically are:
ERROR:HDLCompiler:839 - "M:/ece230/tutorial02/toplevel.vhd" Line 54:
Type std_logic does not match with the integer literal
ERROR:HDLCompiler:839 - "M:/ece230/tutorial02/toplevel.vhd" Line 55:
Type std_logic does not match with the integer literal
ERROR:HDLCompiler:839 - "M:/ece230/tutorial02/toplevel.vhd" Line 56:
Type std_logic does not match with the integer literal
ERROR:HDLCompiler:839 - "M:/ece230/tutorial02/toplevel.vhd" Line 57:
Type std_logic does not match with the integer literal
ERROR:HDLCompiler:854 - "M:/ece230/tutorial02/toplevel.vhd" Line 40:
Unit ignored due to previous errors. VHDL file
Can anyone give a quick suggestion/insight as how to fix this? I tried to troubleshoot it myself, but couldn't identify what was wrong. It appears to me that all the variables are listed as STD_LOGIC...?
Thanks in advance.
1-) I am curious about how ISE synthesizer implements adders in Virtex. I mean what is the smallest adder block size in slices? I was searching Xilinx documentations and I came up with this Virtex-4 FPGA User Guide
On page 204 it says, "The arithmetic logic includes an XOR gate that allows a 2-bit full adder to be implemented within a slice.". But there should be carry lookahead implementation. Because critical path increases logarithmic with the input width.
2-) The other question is, I want to implement long signed vector in VHDL. To achieve higher operating frequencies I want to implement two stage pipelined adder. For example:
signal a, b, c: signed(63 downto 0);
conventional method
c <= a + b;
What I want to implement
signal c_hi : signed(31 downto 0);
signal c_lo : signed(32 downto 0);
process(clk)
begin
if rising_edge (clk) then
--1st stage
c_lo <= ('0' & a(31 downto 0)) + ('0' & b(31 downto 0));
c_hi <= a(63 downto 32) + b(63 downto 32);
--2nd stage
c(63 downto 32) <= c_hi(31 downto 0) + (to_signed(0,31) & c_lo(32 downto 32));
c(31 downto 0) <= c_lo(31 downto 0);
end if;
end process;
But that includes 2x32bit adder + 1x33bit adder. So, what I asking is how can I give the carry out bit of lower addition while summing higher bits?
3-) Is there a way to obtain carry out/overflow bit without increasing width by one.
That's a pipelined adder:
signal a : signed(63 downto 0);
signal b : signed(63 downto 0);
signal c : signed(64 downto 0);
signal sum_stage1 : unsigned(32 downto 0);
process(clk)
begin
if rising_edge(clk) then
-- stage 1: add first 32 bits
sum_stage1 <= ('0' & a(31 downto 0)) + ('0' & b(31 downto 0));
-- stage 2: add next 32 bits (incl. C_in)
c(31 downto 0) <= sum_stage1(31 downto 0); -- optional: align intermediate sums
c(64 downto 32) <= (32 downto 1 => '0') & sum_stage1(sum_stage1'high) +
('0' & a(63 downto 32)) +
('0' & b(63 downto 32));
end if;
end process;
Step 1: add 32 bits (31..0)
Step 2: add 32 bits (63..32) (incl. C_in; C_in = C_out from step 1)
Minimum resources consumption:
2x 32 bit adder or 32 + 33 bit adder if its signed and C_out is relevant
33 bit register
My lab partner and I can't figure out why we're not getting any output in our waveform simulation of this component. We simulated the component by itself and obtained the expected behavior, but nested inside the entity, the output signal was not being initialized and only had uninitialized 'X' response.
This is the component declaration in the top level entity:
99 component CH is
100 Port ( clk : in std_logic;
101 X : in std_logic_vector(31 downto 0);
102 Y : in std_logic_vector(31 downto 0);
103 Z : in std_logic_vector(31 downto 0);
104 CH_OUT : out std_logic_vector(31 downto 0)
105 );
106 end component;
This is the process we use to assign input/output:
289 round_compute2 : process (clk, CH_OUT_sig, e_sig, f_sig, g_sig, T1_sig)
290 begin
291 CH_X_in <= e_sig;
292 CH_Y_in <= f_sig;
293 CH_Z_in <= g_sig;
294 T1_sig <= std_logic_vector(unsigned(CH_OUT_sig));
295 end process;
This is the code for the CH component
1 library IEEE;
2 use IEEE.STD_LOGIC_1164.ALL;
3 use IEEE.STD_LOGIC_ARITH.ALL;
4 use IEEE.STD_LOGIC_UNSIGNED.ALL;
5
6 -- CH is defined as (X AND Y) XOR (X' AND Z)
7 -- Verified working
8
9 entity CH is
10 Port ( clk : in std_logic;
11 X : in std_logic_vector(31 downto 0);
12 Y : in std_logic_vector(31 downto 0);
13 Z : in std_logic_vector(31 downto 0);
14 CH_OUT : out std_logic_vector(31 downto 0)
15 );
16 end CH;
17
18 architecture Behavioral of CH is
19
20 begin
21
22 Compute : process (clk, X, Y, Z)
23 begin
24
25 CH_OUT <= (X and Y) xor ((not X) and Z);
26
27 end process;
28
29 end Behavioral;
These questions are similar, but do not address the issue in this post because-
VHDL component and outputs based on generic
- Does not involve processes
Simple VHDL Problem with synchronous/asynchronous logic
- Does not involve components and signals that are assigned from the system to the component
Why doesn't my code produce output?
- Our code has the correct sensitivity list, I think
You should look through your tool's output for warnings. It sounds like you have an unbound component CH.
With:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- 3 use IEEE.STD_LOGIC_ARITH.ALL;
-- 4 use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- CH is defined as (X AND Y) XOR (X' AND Z)
-- Verified working
entity CH is
Port ( clk : in std_logic;
X : in std_logic_vector(31 downto 0);
Y : in std_logic_vector(31 downto 0);
Z : in std_logic_vector(31 downto 0);
CH_OUT : out std_logic_vector(31 downto 0)
);
end CH;
architecture Behavioral of CH is
begin
Compute : process (clk, X, Y, Z)
begin
CH_OUT <= (X and Y) xor ((not X) and Z);
end process;
end Behavioral;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ch_comp is
end entity;
architecture foo of ch_comp is
component CH is
Port ( clk : in std_logic;
X : in std_logic_vector(31 downto 0);
Y : in std_logic_vector(31 downto 0);
Z : in std_logic_vector(31 downto 0);
CH_OUT : out std_logic_vector(31 downto 0)
);
end component;
signal CH_X_in: std_logic_vector(31 downto 0);
signal CH_Y_in: std_logic_vector(31 downto 0);
signal CH_Z_in: std_logic_vector(31 downto 0);
signal CH_OUT_sig: std_logic_vector(31 downto 0);
signal e_sig: std_logic_vector(31 downto 0) := X"feedface";
signal f_sig: std_logic_vector(31 downto 0) := X"deadbeef";
signal g_sig: std_logic_vector(31 downto 0) := X"ffffffff";
signal T1_sig: std_logic_vector(31 downto 0);
signal clk: std_logic := '0';
begin
round_compute2 : process (clk, CH_OUT_sig, e_sig, f_sig, g_sig) --, T1_sig)
begin
CH_X_in <= e_sig;
CH_Y_in <= f_sig;
CH_Z_in <= g_sig;
T1_sig <= std_logic_vector(unsigned(CH_OUT_sig));
end process;
UUT:
CH
port map (
clk => clk,
X => CH_X_in,
Y => CH_Y_in,
Z => CH_Z_in,
CH_OUT => CH_OUT_sig
);
TEST:
process
begin
wait for 10 ns;
e_sig <= X"deadface";
f_sig <= X"facebeef";
g_sig <= X"EEEEFFFF";
wait for 10 ns;
wait;
end process;
end architecture;
I got:
Which is to say, it appears not to exhibit only uninitialized 'X's on CH_out_sig or T1_sig.
And it would appear you haven't revealed either enough or your VHDL design description or enough of the tool build and simulation process for a third party to see where you went wrong.
I'm a beginner at vhdl and I'm trying to make a 8 bit divider using shift and subtract method. The code for the divider is okay, I guess, but I'm having problems in simulating the inputs. When I use the Verilog test fixture, my inputs which should be (dividend=51 [00110011b], divisor=19 [00010011b]) always end up becoming (dividend=49 [00110001b], divisor=49 [00110001b])) in iSim, and then the outputs (Quotient and remainder = xxxxxxx (unknown)) instead of (quotient=2[00000010b] and remainder=13 [00001101b])...
As I mentioned before, I'm a beginner at vhdl and I've been at this for five hours, I've tried my best to search for a solution online, but failed.... so any help or alternative solution would be greatly appreciated.
I'm using Xilinx ISE 14.3 and iSim.
Here is the code for the 8 bit binary divider.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;
entity division is
generic(SIZE: INTEGER := 8);
port(reset: in STD_LOGIC; --reset
en: in STD_LOGIC; --enable
clk: in STD_LOGIC; --clock
num: in STD_LOGIC_VECTOR((SIZE - 1) downto 0); --dividend
den: in STD_LOGIC_VECTOR((SIZE - 1) downto 0); --divisor
res: out STD_LOGIC_VECTOR((SIZE - 1) downto 0); --result/quotient
rm: out STD_LOGIC_VECTOR((SIZE - 1) downto 0) --remainder
);
end division;
architecture behav of division is
signal bufreg: STD_LOGIC_VECTOR((2 * SIZE - 1) downto 0); --signal array to hold both accumulator and dividend registers as one i.e bufreg(18 bits)
signal dbuf: STD_LOGIC_VECTOR((SIZE - 1) downto 0); --signal array to hold the divisor
signal count: INTEGER range 0 to SIZE; --count to determine when to stop
alias ADreg is bufreg((2 * SIZE - 1) downto SIZE); --ADreg is is alias for top half of bufreg register(17th to 9th bit)
alias DVNDreg is bufreg((SIZE - 1) downto 0); --DVNDreg is is alias for bottom half of bufreg register(8th to 0th bit)
begin
--our process begins here
p_001: process(reset, en, clk)
begin
if reset = '1' then
res <= (others => '0');
rm <= (others => '0');
count <= 0;
elsif rising_edge(clk) then
if en = '1' then
case count is
when 0 =>
ADreg <= (others => '0');
DVNDreg <= num;
dbuf <= den;
res <= DVNDreg;
rm <= ADreg;
count <= count + 1;
when others =>
if bufreg((2 * SIZE - 2) downto (SIZE - 1)) >= dbuf then
ADreg <= '0' & (bufreg((2 * SIZE - 3) downto (SIZE - 1)) - dbuf((SIZE - 2) downto 0));
DVNDreg <= DVNDreg ((SIZE - 2) downto 0) & '1';
else
bufreg <= bufreg((2 * SIZE - 2) downto 0) & '0';
end if;
if count /= SIZE then
count <= count + 1;
else
count <= 0;
end if;
end case;
end if;
end if;
end process;
end behav;
And here is the code for the Verilog test fixture (.v file):
module BINdivisionTEST;
// Inputs
reg reset;
reg en;
reg clk;
reg [7:0] num ;
reg [7:0] den ;
// Outputs
wire [7:0] res;
wire [7:0] rm;
// Instantiate the Unit Under Test (UUT)
division uut (
.reset(reset),
.en(en),
.clk(clk),
.num(num),
.den(den),
.res(res),
.rm(rm)
);
initial begin
// Initialize Inputs
reset = 0;
en = 0;
clk = 0;
//num = 0;
//den = 0;
// Wait 100 ns for global reset to finish
#100;
en = 1;
#100;
clk=1;
num <= "00110011" ;
den <= "00010011" ;
// Add stimulus here
end
endmodule
My biggest problems seem to be initialization of the inputs and probably some mistaken assignments, misuse of the test fixture file and some bad coding.
I should also add that the divider code was compiled in vhdl, ISE 14.3.
I'm extremely sorry if this has been answered before and I don't mean to piss anyone off by uploading bad and amateur code. If this kind of problem has been addressed before could you please provide me with a link.
Again, any help is greatly appreciated.
The simulator may be treating those as strings instead of numbers. Try changing:
num <= "00110011" ;
den <= "00010011" ;
to:
num <= 8'b00110011;
den <= 8'b00010011;
I'm no expert on Verilog but it looks as if you might not be asserting Reset to your VHDL component before testing it.
That would lead "Count" in an uninitialised state so that when you use it, anything could happen and the "XXXX" outputs are a reflection of that.
The reset sequence should look like
En <= '0';
Clk <= '0';
Reset <= '1';
wait for 100 ns;
Reset <= '0';
wait for 100 ns;
-- start testing here
(in VHDL of course ... but it'll translate to Verilog easily)
I have two nested procedures, where the "main" procedure
makes use of "subproc" to accumulates a result in variables
t0 and t1, which is then returned at the end. This should all
be computed in one clock cycle, and the circuit more or less
just consists of simple logic gates (xor, or, and). When I try
to describe the circuit as below I get the following error:
Acutal (variable t0) for formal "a" is not a signal
That makes sense as the subprocure requires signals as input,
but I wanna pass it a variable during the main procedure. Is
there a simple way to circumvent this problem with casting for
example?
Thanks
procedure subproc
(
signal a : in std_logic_vector(31 downto 0);
signal b : in std_logic_vector(31 downto 0);
signal c : in std_logic_vector(31 downto 0);
signal d : in std_logic_vector(31 downto 0);
signal e : out std_logic_vector(31 downto 0);
signal f : out std_logic_vector(31 downto 0)
)
is
variable x : std_logic_vector(31 downto 0);
variable y : std_logic_vector(31 downto 0);
begin
x := (others => '0');
y := (others => '0');
for i in 0 to 31 loop
x(i) := (a(i) xor b(i)) and (c(i) xor d(i));
y(i) := (a(i) xor b(i)) or ((d(i) xor c(i)) xor b(i));
end loop;
e <= x(31 downto 0);
f <= y(31 downto 0);
end;
procedure main
(
signal a : in std_logic_vector(31 downto 0);
signal b : in std_logic_vector(31 downto 0);
signal r : out std_logic_vector(31 downto 0)
)
is
variable res : std_logic_vector(31 downto 0);
variable t0, t1 : std_logic_vector(31 downto 0);
constant c : std_logic_vector(31 downto 0) := X"fedcba90";
constant d : std_logic_vector(31 downto 0) := X"7654321f";
begin
t0 := (others => '0');
t1 := (others => '0');
for i in 0 to 31 loop
if ( (c(i) = '0') && (d(i) = '1') ) then
subproc( t0, t1,
a, b, t0, t1 );
end if;
end loop;
r <= t0;
end;
First off, your "if" clause is written in C-style. You want to say:
if (c(i) = '0') and (d(i) = '1') then
But the problem really is that you describe the procedure as taking SIGNALs as arguments. If you want the results to be assigned to variables, you need to declare a different procedure signature:
procedure subproc (
signal a : in std_logic_vector(31 downto 0);
signal b : in std_logic_vector(31 downto 0);
signal c : in std_logic_vector(31 downto 0);
signal d : in std_logic_vector(31 downto 0);
variable e : out std_logic_vector(31 downto 0);
variable f : out std_logic_vector(31 downto 0))
But then, you also need to change all assignments to e and f, so that they are variable assignments:
e := x(31 downto 0);
Why don't you just define the subproc parameters as variables instead of signals?