Yosys interpret and and not gate as nand for visualization - yosys

Question

I was trying to use yosys purely for visualization in combination with https://github.com/nturley/netlistsvg. A tool which takes a yosys generated json file and creates an SVG out of it. If I have the verilog code:
module test(a,b,c);
input wire a,b;
output wire c;
assign c = ~(a & b);
endmodule
I want to generate an SVG file that has a NAND gate. I use the following Yosys commands:
read_verilog test.v
write_json output.json
Yosys interprests the assign statement as an AND gate and a NOT gate and outputs the following json:
{
"creator": "Yosys 0.7 (git sha1 61f6811, gcc 6.2.0-11ubuntu1 -O2 -fdebug-prefix-map=/build/yosys-OIL3SR/yosys-0.7=. -fstack-protector-strong -fPIC -Os)",
"modules": {
"test": {
"attributes": {
"src": "test.v:1"
},
"ports": {
"a": {
"direction": "input",
"bits": [ 2 ]
},
"b": {
"direction": "input",
"bits": [ 3 ]
},
"c": {
"direction": "output",
"bits": [ 4 ]
}
},
"cells": {
"$not$test.v:4$2": {
"hide_name": 1,
"type": "$not",
"parameters": {
"Y_WIDTH": 1,
"A_WIDTH": 1,
"A_SIGNED": 0
},
"attributes": {
"src": "test.v:4"
},
"port_directions": {
"Y": "output",
"A": "input"
},
"connections": {
"Y": [ 4 ],
"A": [ 5 ]
}
},
"$and$test.v:4$1": {
"hide_name": 1,
"type": "$and",
"parameters": {
"Y_WIDTH": 1,
"B_WIDTH": 1,
"A_WIDTH": 1,
"B_SIGNED": 0,
"A_SIGNED": 0
},
"attributes": {
"src": "test.v:4"
},
"port_directions": {
"Y": "output",
"B": "input",
"A": "input"
},
"connections": {
"Y": [ 5 ],
"B": [ 3 ],
"A": [ 2 ]
}
}
},
"netnames": {
"$not$test.v:4$2_Y": {
"hide_name": 1,
"bits": [ 4 ],
"attributes": {
"src": "test.v:4"
}
},
"$and$test.v:4$1_Y": {
"hide_name": 1,
"bits": [ 5 ],
"attributes": {
"src": "test.v:4"
}
},
"c": {
"hide_name": 0,
"bits": [ 4 ],
"attributes": {
"src": "test.v:3"
}
},
"b": {
"hide_name": 0,
"bits": [ 3 ],
"attributes": {
"src": "test.v:2"
}
},
"a": {
"hide_name": 0,
"bits": [ 2 ],
"attributes": {
"src": "test.v:2"
}
}
}
}
}
}
Is there anyway to force yosys to interpret the line as a nand gate and output json more like this:
{
"creator": "Yosys 0.7 (git sha1 61f6811, gcc 6.2.0-11ubuntu1 -O2 -fdebug-prefix-map=/build/yosys-OIL3SR/yosys-0.7=. -fstack-protector-strong -fPIC -Os)",
"modules": {
"test": {
"attributes": {
"src": "test.v:1"
},
"ports": {
"a": {
"direction": "input",
"bits": [ 2 ]
},
"b": {
"direction": "input",
"bits": [ 3 ]
},
"c": {
"direction": "output",
"bits": [ 4 ]
}
},
"cells": {
"$nand$test.v:4$1": {
"hide_name": 1,
"type": "$nand",
"parameters": {
"Y_WIDTH": 1,
"B_WIDTH": 1,
"A_WIDTH": 1,
"B_SIGNED": 0,
"A_SIGNED": 0
},
"attributes": {
"src": "test.v:4"
},
"port_directions": {
"Y": "output",
"B": "input",
"A": "input"
},
"connections": {
"Y": [ 4 ],
"B": [ 3 ],
"A": [ 2 ]
}
}
},
"netnames": {
"$nand$test.v:4$1_Y": {
"hide_name": 1,
"bits": [ 5 ],
"attributes": {
"src": "test.v:4"
}
},
"c": {
"hide_name": 0,
"bits": [ 4 ],
"attributes": {
"src": "test.v:3"
}
},
"b": {
"hide_name": 0,
"bits": [ 3 ],
"attributes": {
"src": "test.v:2"
}
},
"a": {
"hide_name": 0,
"bits": [ 2 ],
"attributes": {
"src": "test.v:2"
}
}
}
}
}
}
Or is this not something that can be done.

Answer 1

As you have not run any kind of synthesis, the design is still in the form of a word-wide RTL netlist. In this context "$and", "$not" and similar lowercase cells are multibit cells designed to match the Verilog operators.
Running the "synth" command will synthesise your design to a standard set of single-bit gate level cells. This includes a NAND cell. Note that these cells will have uppercase names such as "$_NAND_" and are equivalent to basic logic gates.