I want to share a value on a VI that runs on the computer to a VI that run on myRIO.
I have used global variable and created it in a new VI in my computer section of the myRIO project and use an indicator in a new VI in myRio section, when i run both the value is always zero.
I also tried the shared variable and the value always a zero without a change.
You have to use a Network Published Shared Variable in order to share your variable.
Just some advice, make sure that variable is only being written to in 1 place in your entire system. You can run into interesting race conditions if multiple pieces of code are writing to the same variable.
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I was wondering if there were a way to compute the size of a reg in Verilog. I researched it quite a bit, and found $size(a), but it's only in SystemVerilog, and it won't work in my verilog program.
Does anyone know an alternative for this??
I also wanted to ask as a side note; I'm having some trouble with my test bench in the sense that when I update a value in the file, that change is not taken in consideration when I simulate. I've been told I might have been using an old test bench but the one I am continuously simulating is the only one available in this project.
EDIT:
To give you an idea of what's the problem: in my code there is a "start" signal and when it is set to 1, the operation starts. Otherwise, it stays idle. I began writing the test bench with start=0, tested it and simulated it, then edited the test bench by setting start to 1. But when I simulate it, the start signal remains 0 in the waveform. I tried to check whether I was using another test bench, but it is the only test bench I am using in this project.
Given that I was on a deadline, I worked on the code so that it would adapt to the "frozen" test bench. I am getting now all the results I want, but I wanted to test some other features of my code, so I created a new project and copy pasted the code in new files (including the same test bench). But when I ran a simulation, the waveform displayed wrong results (even though I was using the exact same code in all modules and test bench). Any idea why?
Any help would be appreciated :)
There is a standardised way to do this, but it requires you to use the VPI, which I don't think you get on Modelsim's student edition. In short, you have to write C code, and dynamically link it to the simulator. In the C code, you can get object properties using routines such as vpi_get. Useful properites might be vpiSize, which is what you want, vpiLeftRange, vpiRightRange, and so on.
Having said all that, Verilog is essentially a static language, and objects have to be declared with a static width using constant expressions. Having a run-time method to determine an object's size is therefore of pretty limited value (since you should already know it), and may not solve whatever problem you actually have. Your question would make more sense for VHDL (and SystemVerilog?), which are much more dynamic.
Note on Icarus: the developers have pushed lots of SystemVerilog stuff back into the main language. If you take advantge of this you may find that your code is not portable.
Second part of your question: you need to be specific on what your problem actually is.
Labview is very frusturating to me having used C/Java before.
I have a simple problem I dont know how to solve.
My program does some operations in a loop and updates an indicator inside the loop. I would like to make this loop (and the inputs it requires) into a VI but I have no idea how to make the indicator an output of the VI.
I would like to be able to reuse this VI, connect an indicator to it, and have it automatically update without creating any loops outside of the VI.
In C I would be able to do this by either returning a pointer or passing by reference to a function.
Use a queue to move data between loops in block diagrams.
The producer/consumer pattern uses a queue to move the data between two loops on the same diagram, but a queue is global to a VI hierarchy and by naming it when you create it, a second VI can obtain a reference to it by using the same name.
NB: queues are 1:1 and lossless; if you need 1:N data transmission, use a notifier (which is newest-value lossy) instead.
In LabVIEW while loops have simple condition. The value can go outside the loop only when we will meet the condition. There is a condition terminal in the right down corner of the loop.
At general:
1) When true flag will be set there (stop if true) then the value will be passed outside the loop.
2) When the false flag will be set there (continue if true), then the value will be passed outside the loop.
3) You can always use error wires with condition terminal inside the loop, when error will be raised, then loop will stop.
In your case:
Always try to use the smallest amount of while loops as it is possible due to optimalization reason.
1) You can use while loop in your main VI, while all SubVIs will be in this loop and all values (indicators) will be updated.
2) You can try using while loops inside subVIs, but then you have to provide mechanisms that will transport values outside the loop such as queues or local variables
You can make a reference for a labview indicator as well, but you would need to make it a global variable or pass in the reference from the calling vi.
As for your frustrations, you should know that you can pretty much do anything in Labview that you can do in C.
A) The image below shows how to do this.
B) This style of programming works in small applications, but as an application grows larger, I would encourage you to explore an actual architecture for producing data in one hierarchy and consuming it in another (as alluded to by other answers to this question). In particular, do File >> Create Project and choose the Producer/Consumer template to explore a good starting point for such architectures. There are more sophisticated ones, but that makes an excellent beginning.
I'm trying to pass data which is continuously changed from the inside of one While loop to the inside of another While loop of a sub-vi. The main program on the left is constantly reading new data and the program on the right is adding 1 to the new value. My issue is that I cannot input new values to a While loop which is already running and thus my sub-vi is never updated. I've tried a global variable ("write" from the main program control and then "read" into the sub-vi) but that doesn't work either (same result as if the main were just passing data into the sub).
I apparently don't have enough reputation to post a picture of my program but I'm basically trying to run parallel loops (almost inside each other). Can anyone lend me an experienced hand?
The most common problem with while loops are based on lack of knowledge how exactly does the while loop work in LabVIEW.
First of all the information will be given outside the loop only if the condition terminal (right down corner of the loop) will be flagged as true.
If you want to pass the data earlier (while the loop is running) you have to choose easiest option:
Use queue (is the most common and well working). I can elaborate how this one work in practise if you want, or just try to run an example from LabVIEW help.
local/shared variables - you can define in your own library variables and pass the data by READ/WRITE option.
Please try to upload some documentation to an external server (as you are blocked here), and post a link, and then I could help you with a specific example.
Help»Find Examples. Search for "queue". Pick out an example with parallel loops.
You might want to look into Queues or Notifiers as means of passing data between running loops.
Say I have a variable named repo_path and I want to set some environmental variables or VM options based on this variable, such as SOME_VAR={$repo_path}/some_sub_path or -DsomeProperty={$repo_path} so that I don't have to type repo_path every time I use it. What is the correct way to achieve this other than typing the full address everywhere?
Why don't you define a regular system variable 'REPO_PATH' and use it in IntelliJ Run Configuration as a regular system variable :)
-DsomeProperty=$REPO_PATH
It works well under Mac OS, so I assume it will work under Ubuntu as well.
I'm getting confused of how to place an environmental variable in my head. So it's like a global variable for the operating system? So a global for an IDE is just a reference for something the IDE needs to be able to allocate. Is this the correct idea to have?
At execution each process has an image. It consists of a set of variables in memory that can be accessed, read and modified at all time. It defines the state of a process at a certain point in time.
Some of these variables are created by the process itself for its internal logic, and others will be inherited from its parent process (usually the shell that's used to launch it). They usually describe a certain state of the system. They are called the environment variables. You can use them to define stuff like:
- location of certain executables on your computers (like java or python).
- location of some shared libraries (or DLL if you're on Windows).
- location of the database you're querying
- permission and user access (although that's not the safest place to define it).
The point is, you can define anything in your environment, and every process launched with this environment will inherit from these variables.
I don't know what you mean with the IDE, and quite frankly am not sure I completely understood your question. But since it's been a while and no one answered, I'm hoping it could help you get a beginning of an answer.