STM32 Output MCO configuration - clock

Question

I try to configure my MCO ouput on my STM32f103, only with STD periph lib.
here is my code:
void OutputMCO() {
GPIO_InitTypeDef GPIO_InitStructure;
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
/* Output clock on MCO pin ---------------------------------------------*/
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_Init(GPIOA, &GPIO_InitStructure);
// pick one of the clocks to spew
//RCC_MCOConfig(RCC_MCOSource_SYSCLK); // Put on MCO pin the: System clock selected
//RCC_MCOConfig(RCC_MCOSource_HSE); // Put on MCO pin the: freq. of external crystal
//RCC_MCOConfig(RCC_MCOSource_PLLCLK_Div2); // Put on MCO pin the: System clock selected
}
I have an issue here:
// pick one of the clocks to spew
//RCC_MCOConfig(RCC_MCOSource_SYSCLK); // Put on MCO pin the: System clock selected
//RCC_MCOConfig(RCC_MCOSource_HSE); // Put on MCO pin the: freq. of external crystal
//RCC_MCOConfig(RCC_MCOSource_PLLCLK_Div2); // Put on MCO pin the: System clock selected
None of the 3 possibilities are working on my code. This code was found on internet. Do you know where should I find correct parameters ? The definition of RCC_MCOSource doesn't really help me
Thank you

Answer 1

I found the solution in file stm32f10x_rcc:
#define RCC_MCO_NoClock ((uint8_t)0x00)
#define RCC_MCO_SYSCLK ((uint8_t)0x04)
#define RCC_MCO_HSI ((uint8_t)0x05)
#define RCC_MCO_HSE ((uint8_t)0x06)
#define RCC_MCO_PLLCLK_Div2

Answer 2

For libopencm3 it is a problem of the header files as well.
The configuration bits for which clock should be taken for the MCO are in the Clock configuration register (RCC_CFGR) at position [27:24] (at least for STM32f0 series).
If you now try to configure the MCO to SYSCLK like the following it doesn't work.
RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_MCO_MASK) | RCC_CFGR_MCO_SYSCLK;
If you take a look at the libary file rcc.h you find a line:
#define RCC_CFGR_MCO_SYSCLK 4
so you are writing on bit position 2 instead of 26.
Solution:
RCC_CFGR = (RCC_CFGR & ~(RCC_CFGR_MCO_MASK << 24)) | (RCC_CFGR_MCO_SYSCLK << 24);