I have a couple of errors in my verilog code that pop up when I compile. I believe they are all related. But I can't figure out what the error is. Any help will be greatly appreciated.
The errors are: Two for the input
vlog_a: Error 31004 Syntax error near `input' found
blog_a: Error 31004 Syntax error near 'output' found
module threeBitComparator;
input A2,A1,A0;
input B2,B1,B0;
output E,GE; //E-Equal, GE-Greater than or Equal to
wire X1,X2,X3; //xnor gate
wire Y1,Y2,Y3,Y4,Y5,Y6; // and & or gates
xnor
G1a(X1,A2,B2),
G1b(X2,A1,B1),
G1c(X3,A0,B0);
and
G2a(Y1,A2,~B2),
G2b(Y2,A1,~B1),
G2c(Y3,A0,~B0),
G2d(Y4,X1,Y2),
G2e(Y5,X1,X2,Y3),
G2f(E,X1,X2,X3);
or
G3a(Y6,Y1,Y4,Y5),
G3b(GE,Y6,E);
endmodule
You declared your inputs and outputs but you haven't declared a port list. Your module header needs to look like below code to be IEEE 1364-1995 complaint
module threeBitComparator(A2,A1,A0,B2,B1,B0,E,GE); // <-- port list
input A2,A1,A0;
input B2,B1,B0;
output E,GE; //E-Equal, GE-Greater than or Equal to
Or you can use the ANSI style header introduce in IEEE Std 1364-2001. This style works on any modern Verilog simulator.
module threeBitComparator(
input A2,A1,A0,
input B2,B1,B0,
output E,GE ); //E-Equal, GE-Greater than or Equal to
I think you forgot to declare your input and output in the module port lists. Adding A2, A1..., etc to the port list will solve the compilation errors.
You can check the updated code here.
Related
I am trying to read values from a geoTiff and am using gdallocationinfo for that purpose.
However, when I try to do that, e.g with gdallocationinfo out.tif -wgs85 8.5 47.3, the following error occurs:
root#bc21abca5e07:/usr/src/app# gdallocationinfo out.tif -wgs84 8.5 47.3
ERROR 1: Cannot get geotransform
Note: if I leave the -wgs84 option away, I am able to read the values from the .tif. Also, the -geoloc function is resulting in the same output as -wgs84.
Is this a problem with the geoTiff? I have already tried this command on Windows and on Debian, resulting in the same output both times.
You can't "fix it" short of properly georeferencing your dataset.
The error means that your dataset lacks georeferencing information so GDAL is unable to convert the WGS84 coordinates to pixel coordinates.
I would like to knit the output of my R-markdown, which includes a couple of SQL-chunks. However, if I start knitting, I get the error:
Line 65 Error in eval(expr, envir, enclos) : object 'pp_dataset' not found Calls: <Anonymous> ... process_group.block -> call_block -> eval_lang -> eval Execution halted
I have no clue what is going on, because if I just run this chunk (which starts at line 64) then it works fine.
The chunk that starts at line 64 looks as follows:
```{sql, connection=con, output.var=pp_dataset, error=TRUE, echo=FALSE, include=TRUE}
SELECT
(...)
order by 1,2
```
I've tried several knit-options like error=TRUE/FALSE, echo=TRUE/FALSE and include=TRUE/FALSE but that doesn't work.
Anyone a clue what's wrong?
It looks like you need to quote the dataset name in the rchunk options:
```{sql, connection=con, output.var="pp_dataset", error=TRUE, echo=FALSE,
include=TRUE}
SELECT
(...)
order by 1,2
```
Source: http://rmarkdown.rstudio.com/authoring_knitr_engines.html#sql
I answered the question in this post as well. I'm not sure as to the protocol as the answers are identical.
When rendering your document, Rmarkdown does not have access to your global environment. So you should make sure that all variables that you want to use are defined within the Rmarkdown document, e.g. in a initial chunk:
```{r setup, include=FALSE, warning=FALSE, message=FALSE}
(...)
```
or you should type
render("yourfile.Rmd")
instead of pressing the knit button. In that case, the document does have access to your global environment variables. In this case I guess the 'con' connection is in your global environment, and not found while rendering. Hope this helps!
EDIT: I was able to reproduce the error with your example code:
I was not able to run your code without first initializing the output variable of the SQL statement. In your top-chunck ( so for example below the line setwd(mydirectory), try:
pp_dataset <- NULL
Hope this also solves the issue for you.
I've been testing yosys for some use cases.
Version: Yosys 0.7+200 (git sha1 155a80d, gcc-6.3 6.3.0 -fPIC -Os)
I wrote a simple block which converts gray code to binary:
module gray2bin (gray, bin);
parameter WDT = 3;
input [WDT-1:0] gray;
output [WDT-1:0] bin;
assign bin = {gray[WDT-1], bin[WDT-1:1]^gray[WDT-2:0]};
endmodule
This is an acceptable and valid code in verilog, and there is no loop in it.
It passes compilation and synthesis without any warnings in other tools.
But, when I run in yosys the next commands:
read_verilog gray2bin.v
scc
I get that a logic loop was found:
Found an SCC: $xor$gray2bin.v:11$1
Found 1 SCCs in module gray2bin.
Found 1 SCCs.
The next code, which is equivalent, pass the check:
module gray2bin2 (
gray,
bin
);
parameter WDT = 3;
input [WDT-1:0] gray;
output [WDT-1:0] bin;
assign bin[WDT-1] = gray[WDT-1];
genvar i;
generate
for (i = WDT-2; i>=0; i=i-1) begin : gen_serial_xor
assign bin[i] = bin[i+1]^gray[i];
end
endgenerate
endmodule
Am I missing a flag or synthesis option of some kind?
Using word-wide operators this circuit clearly has a loop (generated with yosys -p 'prep; show' gray2bin.v):
You have to synthesize the circuit to a gate-level representation to get a loop-free version (generated with yosys -p 'synth; splitnets -ports; show' gray2bin.v, the call to splitnets is just there for better visualization):
The answer given by CliffordVienna indeed gives a solution, but I also want to clarify that that it's not suitable to all purposes.
My analysis was done for the purpose of formal verification. Since I replaced the prep to synth to solve the falsely identified logic loops, my formal code got optimized. Wires which I've created that were driven only by the assume property pragma, were removed - this made many assertions redundant.
It's not correct to reduce any logic for the purpose of behavioral verification.
Therefore, if the purpose is to prepare a verification database, I suggest not to use the synth command, but to use a subset of commands the synth command executes.
You can find those commands under:
http://www.clifford.at/yosys/cmd_synth.html
In general, I've used all the commands specified in the above link that do not optimize logic:
hierarchy -check
proc
check
wreduce
alumacc
fsm
memory -nomap
memory_map
techmap
abc -fast
hierarchy -check
stat
check
And everything works as expected.
I am trying to see if Yosys fits my requirements or no.
What i want to do is to find an operation in Verilog code (e.g. temp = 16*val1 + 8*val2 ) and replace this with another op like ( temp = val1 << 4 + val2 << 3 ).
Which parts i need to learn & use from Yosys? if anyone knows the set of command to use, can he/she please let me know to boost my learning curve ?
Thanks.
For example consider the following verilog input (test.v):
module test(input [7:0] val1, val2, output [7:0] temp);
assign temp = 16*val1 + 8*val2;
endmodule
The command yosys -p 'prep; opt -full; show' test.v will produce the following circuit diagram:
And the output written to the console contains this:
3.1. Executing OPT_EXPR pass (perform const folding).
Replacing multiply-by-16 cell `$mul$test.v:2$1' in module `\test' with shift-by-4.
Replacing multiply-by-8 cell `$mul$test.v:2$2' in module `\test' with shift-by-3.
Replacing $shl cell `$mul$test.v:2$1' (B=3'100, SHR=-4) in module `test' with fixed wiring: { \val1 [3:0] 4'0000 }
Replacing $shl cell `$mul$test.v:2$2' (B=2'11, SHR=-3) in module `test' with fixed wiring: { \val2 [4:0] 3'000 }
The two lines reading Replacing multiply-by-* cell are the transformation you mentioned. The two lines after that replace the constant shift operations with wiring, using {val1[3:0], 4'b0000} and {val2[4:0], 3'b000} as inputs for the adder.
This is done in the opt_expr pass. See passes/opt/opt_expr.cc for its source code to see how it's done.
I'm using valgrind to find faults in my code. The command I use is
valgrind --leak-check=yes ./a.out
and I compile the code with -g code alone. I get many errors pointing to a single write line (The three printed values are initialized and well defined).
write (22,*) avlength, stdlength, avenergy
All with the Conditional jump or move depends on uninitialised value(s) error. The said line is the second line from a bunch of lines printing to a single file. At the end of the errors, I get two more, one pointing to the line opening the file
resStep = int(conf*100/iterate)
if (resStep.lt.10) then
write (resFile, "(A5,I1)") "res00",resStep
elseif (ResStep.lt.100) then
write (resFile, "(A4,I2)") "res0",resStep
else
write (resFile, "(A3,I1)") "res",resStep
endif
open (unit=22,file=trim(resFile),status='replace',
c action='write')
resStep is integer. The error is Syscall param write(buf) points to uninitialised byte(s). Finally, I get an error Address 0x52d83f4 is 212 bytes inside a block of size 8,344 alloc'd when I flush the file (before closing it).
I can't find any logic here. If the problem is with opening the file in a faulty way, wouldn't I get the error at the first line?
I use f95 to compile this and my gcc version is 4.1.2. I can't upgrade any of it.
Wild guess: check the data type of resFile. Is it a string or a unit number?
My Fortran 95 is beyond rusty but try moving the call to open() before the calls to write() and pass an integer resUnit instead of resFile as the first argument to write():
CHARACTER(LEN=20):: resFile
INTEGER(KIND=2) :: resUnit, resStep
resStep = 1
resFile = 'MY-results'
resUnit = 22
open (unit=resUnit, file=trim(resFile), status='replace', action='write')
write(resUnit, "(A5,I1)") "res00", resStep
END