Consider the example:
read_verilog ./tests/simple/fsm.v
synth -flatten -top fsm_test
abc -g AND
write_aiger -ascii -symbols hoho.aag
The resulting AIGER file contains input variable clk, which is dangling.
Is it possible to avoid introducing such clock input into AIGER?
Thanks.
Not automatically. The following options exist:
Simply use the SystemVerilog $global_clock feature to avoid having a clock input at all. Use always #($global_clock) instead of always #(posedge clk) and then remove the clk input from your design.
Remove the clock input near the end of your synthesis script. I.e. right before calling write_aiger call something like delete -input fsm_test/clk. This will turn the clock signal into a dangling wire internal to the module. You should avoid doing that before running a lot of optimization commands, or you risk Yosys optimizing away all your FFs. But doing that near the end of your script should be fine.
You can combine 2. with mapping your FFs to $ff/$_FF_ cells (the kind of FF cells generated by $global_clock-blocks). The advantage of this approach is that it makes the clk wire truly unused, so there is no risk of optimizations messing with your FFs because they have an undriven clock input. I've now added a dff2ff.v techmap file in commit e7a984a that simplifies this a bit.
Script for option 2:
read_verilog ./tests/simple/fsm.v
synth -flatten -top fsm_test
abc -g AND
delete -input fsm_test/clk
write_aiger -ascii -symbols hoho.aag
Script for option 3 (requires Yosys git commit e7a984a or later):
read_verilog ./tests/simple/fsm.v
hierarchy -top fsm_test
proc
techmap -map +/dff2ff.v
delete fsm_test/clk
synth -flatten
abc -g AND
write_aiger -ascii -symbols hoho.aag
Related
I'm attempting to use Yosys to generate an edif file that I then use with Vivado tcl scripting to generate a bitstream for an Artix 7 (xc7a15t) FPGA. However, Vivado seems to have trouble with a few of the cells in the edif file.
When I use the same verilog and constraints file completely in Vivado the bitstream is created fine, and it works as expected when I load it onto the FPGA.
I've modeled my workflow off the example here.
Specifically, I'm using the following shell script as a frontend for the yosys and Vivado commands:
#!/bin/bash
yosys run_yosys.ys
vivado -nolog -nojournal -mode batch -source run_vivado.tcl
run_yosys.ys:
read_verilog top.v
synth_xilinx -edif top.edif -top top
run_vivado.tcl
read_xdc top.xdc
read_edif top.edif
link_design -part xc7a15tftg256-1 -top top
opt_design
place_design
route_design
report_utilization
report_timing
write_bitstream -force top.bit
top.v (simple blinky example):
`default_nettype none
module top (
input wire clk,
output reg led);
reg [24:0] cnt = 25'b0;
always #(posedge clk) begin
cnt <= cnt + 1'b1;
if (cnt == 25'b0) begin
led <= !led;
end
else begin
led <= led;
end
end
endmodule // top
top.xdc:
create_clock -period 25.000 -name clk -waveform {0.000 12.500} [get_ports clk]
set_property -dict {IOSTANDARD LVCMOS33 PACKAGE_PIN N11} [get_ports clk]
set_property -dict {IOSTANDARD LVCMOS33 PACKAGE_PIN D1} [get_ports led]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]
The Vivado tcl command opt_design generates the following error:
ERROR: [DRC INBB-3] Black Box Instances: Cell 'GND' of type 'GND/GND' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.
I get the same error for cell 'VCC'.
I also get a warning related to this when calling link_design:
CRITICAL WARNING: [Netlist 29-181] Cell 'GND' defined in file 'top.edif' has pin 'Y' which is not valid on primitive 'GND'. Instance 'GND' will be treated as a black box, not an architecture primitive
Am I using Yosys incorrectly here? What's the correct flow for this? I'm new to Yosys, so forgive me if I've missed something obvious.
I'm using Yosys 0.8+147 and Vivado 2017.2
The solution is in the Yosys user manual. Vivado is complaining about the 'VCC' and 'GND' cells, so we must pass the -nogndvcc option to write_edif. As explained in the description for the -nogndvcc option, to do this we must use hilomap to associate VCC and GND with custom drivers. The full xilinx synthesis is achieved with:
synth_xilinx -top top
hilomap -hicell VCC P -locell GND G
write_edif -nogndvcc top.edif
I'm trying to prove equivalence using miter and sat for a sequential circuit. Essentially, the behavior of the two circuits should be identical as soon as they are reset. I cannot figure out how to tell yosys this though. I have tried reseting the designs with -set in_reset 0 -set-at 0 in_reset 1. Here is an example circuit (a shift register) and yosys script that illustrate what I'm trying to do:
module shift_reg(
input clock,
input reset,
input in,
output out
);
reg [7:0] r;
assign out = r[7];
always #(posedge clock) begin
if (reset)
r <= 0;
else
r <= {r[6:0], in};
end
endmodule
My Yosys commands:
read_verilog shift_reg.v
rename shift_reg shift_reg_2
read_verilog shift_reg.v
prep; proc; opt; memory
miter -equiv -flatten shift_reg shift_reg_2 miter
hierarchy -top miter
sat -verify -tempinduct -prove trigger 0 -set in_reset 0 -set-at 0 in_reset 1 -seq 0 miter
If I add -set-init-zero it works, but that defeats the purpose because I'm trying to test reset behavior. I can also change -seq 0 to -seq 8 but that also defeats the purpose because I'm trying to check that the circuits are equivalent as soon as they are reset.
How do I tell equivalence checking to reset the circuits before checking?
Simply use the following SAT command:
sat -verify -tempinduct -prove trigger 0 \
-set in_reset 0 -set-at 1 in_reset 1 -seq 1 miter
Changes compared to your script:
The "sat" command numbers steps starting with 1. So the -set-at option needs 1 as first argument for resetting in the first cycle.
The "-seq 1" will disable checking of properties in the first cycle. This make sense because the reset will only have taken effect in the 2nd cycle, so the two modules might indeed produce different outputs in cycle 1.
I know yosys has limited tri-state support, but I'm looking for a possible workaround.
The following circuit:
module TBUF2
(
inout SALIDA1,
inout SALIDA2,
input OE,
output C);
assign SALIDA1=OE ? 1'b0 : 1'bZ;
assign SALIDA2=OE ? 1'b0 : 1'bZ;
wire e;
assign e=SALIDA1 & SALIDA2;
assign C=e;
endmodule
Is interpreted as:
TBUF2 parsed tree
Note that when OE is 0 C=SALIDA1 and SALIDA2.
During the opt pass, the opt_merge pass removes $2 mux and generates:
TBUF2 optimized
This breaks the circuit (when OE is 0 then C=SALIDA1). I realize this is because yosys/ABC doesn't really understand the consequences of the "1'z" input.
Is it possible to keep muxes that meet the following criteria?:
1) At least one input is 1'Z
2) Its output drives an inout pin
Here is the script to reproduce it:
read_verilog tbuf2.v
proc
show -format dot -prefix tbuf2_01
opt
show -format dot -prefix tbuf2_02
Convert the tristate buffer $mux cells to $tribuf cells by running the tribuf command after proc and before running any opt commands.
I've been testing yosys for some use cases.
Version: Yosys 0.7+200 (git sha1 155a80d, gcc-6.3 6.3.0 -fPIC -Os)
I wrote a simple block which converts gray code to binary:
module gray2bin (gray, bin);
parameter WDT = 3;
input [WDT-1:0] gray;
output [WDT-1:0] bin;
assign bin = {gray[WDT-1], bin[WDT-1:1]^gray[WDT-2:0]};
endmodule
This is an acceptable and valid code in verilog, and there is no loop in it.
It passes compilation and synthesis without any warnings in other tools.
But, when I run in yosys the next commands:
read_verilog gray2bin.v
scc
I get that a logic loop was found:
Found an SCC: $xor$gray2bin.v:11$1
Found 1 SCCs in module gray2bin.
Found 1 SCCs.
The next code, which is equivalent, pass the check:
module gray2bin2 (
gray,
bin
);
parameter WDT = 3;
input [WDT-1:0] gray;
output [WDT-1:0] bin;
assign bin[WDT-1] = gray[WDT-1];
genvar i;
generate
for (i = WDT-2; i>=0; i=i-1) begin : gen_serial_xor
assign bin[i] = bin[i+1]^gray[i];
end
endgenerate
endmodule
Am I missing a flag or synthesis option of some kind?
Using word-wide operators this circuit clearly has a loop (generated with yosys -p 'prep; show' gray2bin.v):
You have to synthesize the circuit to a gate-level representation to get a loop-free version (generated with yosys -p 'synth; splitnets -ports; show' gray2bin.v, the call to splitnets is just there for better visualization):
The answer given by CliffordVienna indeed gives a solution, but I also want to clarify that that it's not suitable to all purposes.
My analysis was done for the purpose of formal verification. Since I replaced the prep to synth to solve the falsely identified logic loops, my formal code got optimized. Wires which I've created that were driven only by the assume property pragma, were removed - this made many assertions redundant.
It's not correct to reduce any logic for the purpose of behavioral verification.
Therefore, if the purpose is to prepare a verification database, I suggest not to use the synth command, but to use a subset of commands the synth command executes.
You can find those commands under:
http://www.clifford.at/yosys/cmd_synth.html
In general, I've used all the commands specified in the above link that do not optimize logic:
hierarchy -check
proc
check
wreduce
alumacc
fsm
memory -nomap
memory_map
techmap
abc -fast
hierarchy -check
stat
check
And everything works as expected.
I was wondering if it is possible to access debug information in a running application that has been compiled with /DEBUG (Pascal and/or C), in order to retrieve information about structures used in the application.
The application can always ask the debugger to do something using SS$_DEBUG. If you send a list of commands that end with GO then the application will continue running after the debugger does its thing. I've used it to dump a bunch of structures formatted neatly without bothering to write the code.
ANALYZE/IMAGE can be used to examine the debugger data in the image file without running the application.
Although you may not see the nice debugger information, you can always look into a running program's data with ANALYZE/SYSTEM .. SET PROCESS ... EXAMINE ....
The SDA SEARCH command may come in handy to 'find' recognizable morcels of date, like a record that you know the program must have read.
Also check out FORMAT/TYPE=block-type, but to make use of data you'll have to compile your structures into .STB files.
When using SDA, you may want to try run the program yourself interactively in an other session to get sample sample addresses to work from.... easier than a link map!
If you programs use RMS a bunch (mine always do :-), then SDA> SHOW PROC/RMS=(FAB,RAB) may give handy addresses for record and key buffers, allthough those may also we managed by the RTL's and thus not be meaningful to you.
Too long for a comment ...
As far as I know, structure information about elements is not in the global symbol table.
What I did, on Linux, but that should work on VMS/ELF files as well:
$ cat tests.c
struct {
int ii;
short ss;
float ff;
char cc;
double dd;
char bb:1;
void *pp;
} theStruct;
...
$ cc -g -c tests.c
$ ../extruct/extruct
-e-insarg, supply an ELF object file.
Usage: ../extruct/extruct [OPTION]... elf-file variable
Display offset and size of members of the named struct/union variable
extracted from the dwarf info in the elf file.
Options are:
-b bit offsets and bit sizes for all members
-lLEVEL display level for nested structures
-n only the member names
-t print base types
$ ../extruct/extruct -t ./tests.o theStruct
size of theStruct: 0x20
offset size type name
0x0000 0x0004 int ii
0x0004 0x0002 short int ss
0x0008 0x0004 float ff
0x000c 0x0001 char cc
0x0010 0x0008 double dd
0x0018 0x0001 char bb:1
0x001c 0x0004 pp
$