I made at .bat file that modifies a .h file containing a #define BUILD_VER so that it gets incremented every time I build.
There is also a #define MAJOR_VER in the same .h file that defines the version that the customers will see.
I'm trying to figure out a way to get the MAJOR_VER and BUILD_VER attached the to the binary output file (I'm using MSP430's so the output is a .txt files.)
So with something like this
#define MAJOR_VER 22
#define BUILD_VER 4321
...and building "Project_A"
"Project_A.txt" <== current default behaviour
"Project_A_V22_4321.txt" <==What I'm looking for
It would be nice if I could set an IDE variable using these #defines somehow.
This posts answers how to create custom IDE variables, which I didn't see the last time I started looking into this IAR project variable like $PROJ_DIR$
I know I could just write another .bat script to modify the file name, but this seems cleaner to me. And a little more obvious if I were new to the project.
Any thoughts?
Related
Alright so I'm using the "Catch2" framework for C++ Unit Testing and in my "testMain.cpp" (Doesn't matter) I include the single header version of it #include "Catch.hpp".
The problem is every time I write just a small test, I have to compile the program in order to see the outputs again. But the single header is something like 70000 lines and it takes FOREVER.
I understand that with source files you can simply compile them into object files and after that link them. So if you are using the same source file for just linking there is no really a need to recompile it over again.
So the point of this question is, Is it possible to somehow compile the Catch.hpp file and just use it as a link after words? Or in order to slow it down do I have to get the multi-header version of the framework?
Thanks in Advance!
Have you read https://github.com/catchorg/Catch2/blob/devel/docs/slow-compiles.md ?
It is recommended to move the tests main function to a separate file, so that the compile intensive parts are only compiled once.
I am trying to figure out how to modularize my program. I probably should not be, since I am only beginner trying to write code for Arduino. BUT, putting it all in one file is driving me batty.
I have an .INO file. I can make it compile with pinMode and digitalWrite commands in it. If I move that code to a .CPP file, I get errors that OUTPUT, HIGH, LOW, INPUT_PULLUP are not declared in this scope. I have tried including files I thought might contain the definitions but nothing is working.
How do I make this work?
I ADDED THIS TO THE FILES AND IT APPEARS TO WORK
#include <arduino.h>
I am using CMake to link and build my C++ project, and in said project I am using the fstream library to read from a file. However, when passing the path of the file to my code, I am forced to use a long string such as "../../../../folder/folder/folder/file" to properly reference which file I want opened. I presume this is because my .exe that CMake creates is buried deep, "far" away from my source code, which is why I would have to backtrack so much.
I am wondering if there is something I could put in my CMakeLists.txt to potentially allow for the shortening of this inclusion path.
To save myself some time I have not included my file structure as of now, but if it is needed in order for a solution to be formed I certainly can edit and add it in. I do not necessarily need a case-specific solution, rather just a generalized method in which I could go about doing this.
It looks like CMake doesn't provide such functionality , CMake doesn't do much with execution of your application.
So, For solution you have following
can either create a shell script to copy the file into the desired location which can be picked by the executable and shell script can be run while make process
pass it as a commandline argument to your c++ executable.
create a macro with this location and use this macro in the source file : - CMake can help you in this
Using add_compile_definitions( ...)
I have a Config.h file which includes various preprocessor conditionals based on the environment. The project has 2 targets. Via the preprocessor arguments, if the environment is the first target we may have BASE_URL = #"https://firsttarget.com/", whereas if the environment is the second target we may have BASE_URL = #"https://secondtarget.com/".
For legal purposes, if someone were to recompile the assembly, and go hunting to strings etc... we cannot have somebody finding the string #"https://firsttarget.com/" if they were looking into the binary for the second target app.
So my question is... are strings behind preprocessor conditionals removed during Archive if they are not relevant?
Sections in code between #ifdef and #endif (or #else) are not seen by the compiler unless the symbol given on the ifdef line is defined. You can easily show this by writing something that won't compile in such a section. And since the compiler doesn't see that code there is no way the value of that define can end up in the binary.
To see exactly what the compiler will work with you can select an implementation file in Xcode and chose "Product > Perform Action > Preprocess" from the menu. This will show you exactly what the compiler will work with. Of course there will also be the content from all the system .h files that are imported, so your code most likely is at the very end. Your #define lines will be stripped too, so to really check which strings will be used you need to chose a file that actually uses those macros.
And finally you can do the same thing an attacker might do - use the strings utility on the compiled binary and see what's in there. In Xcode build your app and select the "Show in Finder" option for your app bundle from the products group. There select "Show package contents" to open app your actual app bundle. The actual binary is in there with the same name as your bundle but no file extension. Then open a terminal window, type "strings " (that is the word strings followed by a space) and drag the binary on top of this. Then confirm with return. You will get a long list of every readable string from the binary (including every selector).
I've used simple makefiles for years, but only recently been assigned the task of learning the ins and outs of a large, complicated set of Autotools-generated makefiles which is used for a code base my employer has bought. In these, I'm running into variable declarations like the following:
QOBJECT_MOCSRCS = $(QOBJECT_HEADER:%.h=.gen/moc_%.cpp) \
$(QOBJECT_SRCS:%.cpp=.gen/moc_%.cpp)
QOBJECT_DEPS = $(QOBJECT_MOCSRCS:%.cpp=.deps/%.Po)
My best guess from context is that these set up lists of names of files to be provided by the build process, eg., QOBJECT_MOCSRCS should end up as a list of (a) .h files, (b) .cpp files, based on the % stem names of a set of intermediate .cpp files which will be generated during the build, in a temporary directory ./gen. This is used to store the moc_%.cpp files which are output as a result of a build of Qt files with Qt's moc tool...what is driving me crazy, is that I have been unable to find anything in any make documentation I've got (mostly the GNU make manual) that tells me what this style of declaration is called, so I can track it down and get a grip on the syntax. The contents of the $() look sort of like rules, and the nearest equivalents in the GNU make manual seem to be rules specifying target-specific variable values, but I have no idea whether this is anywhere near a correct reading. Can anyone point me to an appropriate reference for study?
This feature is called substitution references, http://www.gnu.org/software/make/manual/html_node/Substitution-Refs.html#Substitution-Refs