VHDL: Signals get U value even though there is another value assigned - testing

Question

I’m implementing IDEA algorithm using VHDL, I have a problem in my
keygenerator module, when I run the simulator I get values U in all of
the signals even though I assign other values to them.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity keygenerator is
Port ( round : in STD_LOGIC_VECTOR (3 downto 0);
key : in STD_LOGIC_VECTOR (127 downto 0);
keyout1 : out STD_LOGIC_VECTOR (15 downto 0);
keyout2 : out STD_LOGIC_VECTOR (15 downto 0);
keyout3 : out STD_LOGIC_VECTOR (15 downto 0);
keyout4 : out STD_LOGIC_VECTOR (15 downto 0);
keyout5 : out STD_LOGIC_VECTOR (15 downto 0);
keyout6 : out STD_LOGIC_VECTOR (15 downto 0));
end keygenerator;
architecture Behavioral of keygenerator is
SIGNAL key0 : std_logic_vector (127 downto 0);
SIGNAL key1 : std_logic_vector (127 downto 0);
SIGNAL key2 : std_logic_vector (127 downto 0);
SIGNAL key3 : std_logic_vector (127 downto 0);
SIGNAL key4 : std_logic_vector (127 downto 0);
SIGNAL key5 : std_logic_vector (127 downto 0);
SIGNAL key6 : std_logic_vector (95 downto 0);
signal output : std_logic_vector (95 downto 0);
begin
process (round, key)
begin
key0 <= key;
key1 <= key0(102 downto 0) & key0(127 downto 103);
key2 <= key1(102 downto 0) & key1(127 downto 103);
key3 <= key2(102 downto 0) & key2(127 downto 103);
key4 <= key3(102 downto 0) & key3(127 downto 103);
key5 <= key4(102 downto 0) & key4(127 downto 103);
key6 <= key5(102 downto 7);
case round is
when "0000" => output <= key0(127 downto 32);
when "0001" => output <= key0(31 downto 0) & key1(127 downto 64);
when "0010" => output <= key1(63 downto 0) & key2(127 downto 96);
when "0011" => output <= key2(95 downto 0);
when "0100" => output <= key3(127 downto 32);
when "0101" => output <= key3(31 downto 0) & key4(127 downto 64);
when "0110" => output <= key4(63 downto 0) & key5(127 downto 96);
when "0111" => output <= key5(95 downto 0);
when "1000" => output <= key6;
when others => output <= (others => 'X');
end case;
end process;
keyout6 <= output(15 downto 0);
keyout5 <= output(31 downto 16);
keyout4 <= output(47 downto 32);
keyout3 <= output(63 downto 48);
keyout2 <= output(79 downto 64);
keyout1 <= output(95 downto 80);
end Behavioral;
That's my testbench:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: keygenerator
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_keygenerator IS
END tb_keygenerator;
ARCHITECTURE behavior OF tb_keygenerator IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT keygenerator
PORT(
round : IN std_logic_vector(3 downto 0);
key : IN std_logic_vector(127 downto 0);
keyout1 : OUT std_logic_vector(15 downto 0);
keyout2 : OUT std_logic_vector(15 downto 0);
keyout3 : OUT std_logic_vector(15 downto 0);
keyout4 : OUT std_logic_vector(15 downto 0);
keyout5 : OUT std_logic_vector(15 downto 0);
keyout6 : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal round : std_logic_vector(3 downto 0) := (others => '0');
signal key : std_logic_vector(127 downto 0) := (others => '0');
--Outputs
signal out1 : std_logic_vector(15 downto 0);
signal out2 : std_logic_vector(15 downto 0);
signal out3 : std_logic_vector(15 downto 0);
signal out4 : std_logic_vector(15 downto 0);
signal out5 : std_logic_vector(15 downto 0);
signal out6 : std_logic_vector(15 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
constant I_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: keygenerator PORT MAP (
round => round,
key => key,
keyout1 => out1,
keyout2 => out2,
keyout3 => out3,
keyout4 => out4,
keyout5 => out5,
keyout6 => out6
);
-- Clock process definitions
I_process :process
begin
key <= X"12345678912345678912345678912345";
round <="1100";
wait for I_period/2;
key <= X"12345678912345678912345678912345";
round <="1001";
wait for I_period/2;
end process;
END;