Modesim VHDL testbench - testing

Question

I have a problem: I've tried to simulate my project by the testbench, but ModelSim wrote this message:
Error: C:/.../testbench.vhd(62): (vcom-1136) Unknown identifier "arst".
And the same message for each other ports of testbench's component.
Also, next one type of messages, for internal signals of testbench:
Error: C:/.../testbench.vhd(63): (vcom-1484) Unknown formal identifier ARST_STIM
Top-entity top_test and each other entities in one common folder with testbench, so I do not understand what is a reason of the problem. I've posted the code of my testbench below:
-- Created:
-- by - Desmond.UNKNOWN (DESMOND-PC)
-- at - 00:52:37 07.03.2016
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY testbench IS
END testbench;
ARCHITECTURE rtl OF testbench IS
-- Architecture declarations
-- Internal signal declarations
-- Component declarations
COMPONENT top_test
PORT (
arst : IN std_logic;
bithigh : IN std_logic_vector(31 DOWNTO 0);
bitlow : IN std_logic_vector(31 DOWNTO 0);
ca_bh10 : OUT std_logic;
ch_ca_data : IN std_logic_vector(31 DOWNTO 0);
ch_s : IN std_logic_vector(31 DOWNTO 0);
clk120MHz : IN std_logic;
clk240Mhz : IN std_logic;
clock_value_high : IN std_logic_vector(31 DOWNTO 0);
clock_value_low : IN std_logic_vector(31 DOWNTO 0);
dac_1 : OUT std_logic_vector(15 downto 0);
dac_2 : OUT std_logic_vector(15 downto 0);
freq_setup : IN std_logic_vector(31 DOWNTO 0);
led : OUT std_logic;
level : IN std_logic_vector(31 DOWNTO 0);
out_symb : OUT std_logic;
pps : IN std_logic
);
END COMPONENT;
--------------------------------------
signal LED,CA_OUT,MOD_OUT : std_logic;
signal ARST_STIM,CLK_120MHZ,CLK_240MHZ,PPS_STIM : std_logic := '0';
signal BIT_HIGH_STIM,BIT_LOW_STIM,LEVEL_STIM,CA_DATA_STIM,FREQ_STIM,CLK_LOW_STIM,CLK_HIGH_STIM,CH_SELECT_STIM : std_logic_vector (31 downto 0);
signal DAC_1, DAC_2 : std_logic_vector (15 downto 0);
--------------------------------------
constant CLK_120MHZ_PERIOD : TIME := 8.33 ns;
constant CLK_240MHZ_PERIOD : TIME := 4.15 ns;
-------------------------------------
BEGIN
U_0 : top_test
PORT MAP (
ARST_STIM => arst,
CLK_120MHZ => clk120MHz ,
CLK_240MHZ => clk240Mhz,
PPS_STIM => pps,
BIT_HIGH_STIM => bithigh ,
BIT_LOW_STIM => bitlow,
LEVEL_STIM => level,
CA_DATA_STIM => ch_ca_data,
FREQ_STIM => freq_setup,
CLK_LOW_STIM => clock_value_low,
CLK_HIGH_STIM => clock_value_high,
CH_SELECT_STIM => ch_s,
DAC_1 => dac_1,
DAC_2 => dac_2,
CA_OUT => ca_bh10,
LED => led,
MOD_OUT => out_symb
);
--------------------------
CLK_GENERATION : process
begin
CLK_120MHZ <= not CLK_120MHZ after (CLK_120MHZ_PERIOD/2);
CLK_240MHZ <= not CLK_240MHZ after (CLK_240MHZ_PERIOD/2);
end process CLK_GENERATION;
----------------------------
STIM_PROC : process
begin
ARST_STIM <= '1';
PPS_STIM <= '0';
wait for 100 ns;
CH_SELECT_STIM <= (others=>'0');
CLK_LOW_STIM <= "00010111010110001110001000011001";
CLK_HIGH_STIM <= "00000000000000000000000000000001";
FREQ_STIM <= "00000010001000100010001000100010";
LEVEL_STIM <= "00000000000000000000000000110010";
CA_DATA_STIM <= "00000000000000000000000000000110";
BIT_LOW_STIM <= "00100110100101111011000000000000";
BIT_HIGH_STIM <= "10101010010010111110100001010101";
wait for 1800 ns;
PPS_STIM <= '1';
wait for 100 ns;
PPS_STIM <= '0';
wait for 1000 ns;
CH_SELECT_STIM <= "00000000000000000000000000000001";
wait for 999999000 ns;
PPS_STIM <= '1';
wait for 100 ns;
PPS_STIM <= '0';
wait for 10000000 ns;
end process STIM_PROC;
END rtl;