Behavioral into FlipFlop Structural - process

Question

In this code, when reset equals 1 the s becomes 1000 and when reset equals 0 the s becomes 0100 then 0010 then 0001 and it starts all over again with 1000 as the start value, only if the clock is up.
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clock_behav is
port (clock : in std_logic;
reset : in std_logic;
s : out std_logic_vector (3 downto 0));
end clock_behav;
architecture behav of clock_behav is
begin
process(clock,reset)
variable shift_counter: integer := 0;
begin
if (reset='1') then
s<="1000";
shift_counter := 1;
else
if(clock'event and clock='1') then
if(shift_counter =1) then
s<="0100";
shift_counter := 2;
elsif(shift_counter =2) then
s<="0010";
shift_counter := 3;
elsif(shift_counter =3) then
s<="0001";
shift_counter := 0;
else
s<="1000";
shift_counter := 1;
end if;
end if;
end if;
end process;
end behav;
I want to create this
With FlipFlops as you can see, one Set and 3 Reset. But, I struggle to move from behavioral into structural, because in VHDL we can't have in process port maps. Of course I tried many things, as you can see below, but it's impossible to recreate it with flipflops if the port maps are not inside the process. As you can clearly understand , my knowledge about VHDL it's not that great. Also, I want you to tell me if I did right when I changed the flipflop D and Q types, it was std_logic and I changed it to std_logic_vector . I did this for the purpose of this exercise.
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clock_structural is
port (clock : in std_logic;
reset : in std_logic;
s : out std_logic_vector (3 downto 0));
end clock_structural;
architecture behavior of clock_structural is
signal t,t1,t2,t3 : std_logic_vector (3 downto 0);
component flipflop_new
port
(D : in std_logic_vector (3 downto 0);
CLK : in std_logic;
CLR : in std_logic;
Q : out std_logic_vector (3 downto 0));
end component;
component flipflop_set
port
(D_s : in std_logic_vector (3 downto 0);
CLK_s : in std_logic;
CLR_s : in std_logic;
Q_s : out std_logic_vector (3 downto 0));
end component;
begin
process(clock,reset)
variable shift_counter: integer := 0;
begin
if (reset='1') then
t<="1000";
shift_counter := 1;
else
if(clock'event and clock='1') then
if(shift_counter =1) then
shift_counter := 2;
elsif(shift_counter =2) then
shift_counter := 3;
elsif(shift_counter =3) then
shift_counter := 0;
else
shift_counter := 1;
end if;
end if;
end if;
end process;
FFS1: flipflop_set port map(t,clock,reset,t1);
s<=t1;
FFR1: flipflop_new port map(t1,clock, reset,t2);
s<=t2;
FFR2: flipflop_new port map(t2,clock, reset,t3);
s<=t3;
FFR3: flipflop_new port map(t3,clock, reset,s);
end behavior ;
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity flipflop_new is
port ( D : in std_logic_vector (3 downto 0);
CLK : in std_logic;
CLR : in std_logic;
Q : out std_logic_vector (3 downto 0)
);
end flipflop_new;
architecture behavior of flipflop_new is
begin
process(CLK)
begin
if CLR='0' then null;
elsif RISING_EDGE(CLK) then
Q <= D;
end if;
end process ;
end behavior ;
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity flipflop_set is
port ( D_s : in std_logic_vector (3 downto 0);
CLK_s : in std_logic;
CLR_s : in std_logic;
Q_s : out std_logic_vector (3 downto 0)
);
end flipflop_set;
architecture behavior of flipflop_set is
begin
process(CLK_s)
begin
if CLR_s='1' then null;
elsif RISING_EDGE(CLK_s) then
Q_s <= D_s;
end if;
end process ;
end behavior ;

Answer 1

There are several things to change or improve. A structural VHDL model should describe your schematic, which you don't really do.
First, why do you have shift_counter in your structural? You don't need that process.
Second, you instantiate 4 of your flip-flop entity which are each 4 bits wide, while your schematic's has 4 flip-flops. Basically, you instantiate a total of 16 registers when you need 4. Why is your flip-flop model 4 bits wide? It should be a single bit.
Third, look at your flip-flop description:
process(CLK)
begin
if CLR='0' then
null;
elsif RISING_EDGE(CLK) then
Q <= D;
end if;
end process ;
Does it seems what a flip-flop do? The Q <= D when the clock rises is fine, but does nothing happens when the clr of the flip-flop is active? Your output should reset/set in that case, which is not what your VHDL describe.
Another error is that you assign your output s 3 times. s must be assigned once, but you can assign bit individually like s(0) <= t1.
Finally, you don't describe the feedback. The output of your last flip-flop is s, while the input of the first flip-flop is t. From your schematic, they should be connected together.