I have such a connection in my topology:
https://courses.cs.ttu.ee/w/images/e/e5/ITI0130_Lab3_IEEE1394.pdf
I have written such a declaration to run a simulation on uppaal:
const int N=7;
const int d1=1;
const int d2=2;
const int d3=3;
typedef int[0,N] id_t;
id_t Id;
const bool nb[N+1][N+1]=
{
{0,0,0,0,0,0,0,0},
{0,0,1,0,1,1,0,0},
{0,1,0,1,0,0,1,0},
{0,0,1,0,0,0,0,0},
{0,1,0,0,0,0,0,0},
{0,1,0,0,0,0,0,0},
{1,0,1,0,0,0,0,1},
{0,0,0,0,0,0,1,0}
};
urgent chan req[N+1];
urgent chan ack[N+1];
id_t req_[N+1], ack_[N+1];
The array specifies the connection of nodes with indexes. For instance, node "0" is not connected with any node, so it has 0 in all the indexes. But node "1" is connected with node "2, 4, 5". So it has 1 in that indexes.
Now I get two leaders when I run the simulation.
I have to connect node "0" to the topology to get one leader when I run the simulation.
I have tried to connect node "0" to some nodes, but it hasn't worked.
This is my model:
How can I manage to do this?
Related
I have connected 2 TI controllers via SPI. The TMS320F28055 controller is my master and the TMS320F2885 controller is my slave. I want to send complete data to the slave via spi. The data always ends up successfully in the SPIDAT register, i.e. the shift register. The shift register should then send the data to the SPIRXBUF - Buffer. Sometimes the data is successfully sent to the buffer and sometimes not it's always very random I've tried a lot. I don't use a FIFO. Does anyone know how I can fix the problem.
I made a table showing the data in the master and slave registers. I also send the configuration of the slave and master.
void spi_init(void)
{
SpiaRegs.SPICTL.all = 0x000E; //Normal SPI clocking scheme(Data in latch on rising edge)master, 4-pin option, No interrupt
SpiaRegs.SPICTL.bit.CLK_PHASE = 1; //1
SpiaRegs.SPIBRR = 0x0077; //BateRate 0.5MHz
SpiaRegs.SPICCR.all = 0x0087; //SPI is ready to transmit or receive the next character.
SpiaRegs.SPICCR.bit.CLKPOLARITY = 0; //0
SpiaRegs.SPIPRI.bit.FREE = 1;
}
This is the code from my master, I use the TMS320F28055:
void spi_init(void)
{
SpiaRegs.SPICCR.bit.SPISWRESET = 0;
SpiaRegs.SPICTL.all = 0x000A; //8 //Normal SPI clocking scheme(Data in latch on rising edge)slave, 4-pin option, No interrupt
SpiaRegs.SPICTL.bit.CLK_PHASE = 1; //1
SpiaRegs.SPIBRR = 0x0077; //BateRate 0.5MHz ist für den Slave nicht notwendig
SpiaRegs.SPICCR.all = 0x0087; //SPI is ready to transmit or receive the next character.
SpiaRegs.SPICCR.bit.CLKPOLARITY = 0; //0
SpiaRegs.SPICTL.bit.SPIINTENA = 1 ;
SpiaRegs.SPICTL.bit.OVERRUNINTENA = 1 ;
SpiaRegs.SPIPRI.bit.FREE = 1;
SpiaRegs.SPICCR.bit.SPISWRESET=1;
}
And this is the code from my slave TMS320F28035.
I'm using an interrupt here, but I've also tried it without an interrupt.
uint16_t pdata = 0x1234;
int dataH, dataL;
dataH = 0;
dataL = 0;
dataH = (pdata >> 8);
dataL = (pdata & 0x00FF);
spi_xmit(dataH);
spi_xmit(dataL);
And with that I send example data, in this case it would be the 0x1234. When I send it it arrives successfully in the shift register and buffer. But if I want to send it more often, the shift register does not completely shift the data into the buffer. To check I debug both microcontrollers at the same time. By the way, I send 8 bits twice in a row. the buffer has a size of 16 bits.
I am following netlink example on this question and answer.
But, I don't see a sort of connection identifier in source codes. Say:
Kernel
my_nl_sock = netlink_kernel_create(&init_net, NETLINK_USERSOCK, 0,
my_nl_rcv_msg, NULL, THIS_MODULE);
User space
nls = nl_socket_alloc();
ret = nl_connect(nls, NETLINK_USERSOCK);
ret = nl_send_simple(nls, MY_MSG_TYPE, 0, msg, sizeof(msg));
where NETLINK_USERSOCK and MY_MSG_TYPE don't seem to be a connection identifier.
In such a case, how does netlink know which data comes from which user space app or kernel module and which user space app or kernel module the data should go?
In my guess, netlink receives data from user space app or kernel module and broadcasts it. And every netlink-connected app or module checks message type if data is destined to 'me'
Is what I think right?
Firstly, I recommend to read some doc, for example http://www.linuxfoundation.org/collaborate/workgroups/networking/generic_netlink_howto
To communicate you have to register a family with supported operations. It can be done with the following functions
int genl_register_family( struct genl_family *family)
int genl_register_ops( struct genl_family * family, struct genl_ops *ops)
An example of a family definition:
/*
* Attributes (variables): the index in this enum is used as a reference for the type,
* userspace application has to indicate the corresponding type
*/
enum {
CTRL_ATT_R_UNSPEC = 0,
CTRL_ATT_CNT_SESSIONS,
__CTRL_ATT_R_MAX
};
#define CTRL_ATT_R_MAX ( __CTRL_ATT_R_MAX - 1 )
#define CTRL_FAMILY "your-family"
#define CTRL_PROTO_VERSION 1
/* Family definition */
static struct genl_family ctrl_bin_gnl_family = {
.id = GENL_ID_GENERATE, // genetlink should generate an id
.hdrsize = 0,
.name = CTRL_FAMILY, // the name of this family, used by userspace application
.version = CTRL_PROTO_VERSION, // version number
.maxattr = CTRL_ATT_R_MAX, // max number of attr
};
An example of an operation definition:
struct genl_ops ctrl_info = {
.cmd = CTRL_CMD_INFO,
.flags = 0,
.policy = 0, // you can use policy if you need
.doit = 0, // set this callback if this op does some interval stuff
.dumpit = __info, // set this callback if this op dump data
};
After that you can use in your userspace app your family and operations to communicate. Make a connection:
struct nl_sock * _nl = nl_socket_alloc();
int ret = genl_connect(nl);
// test if fail
int gid = genl_ctrl_resolve( nl, CTRL_FAMILY );
// test if fail
Send info operation
struct nl_msg * msg = msg_alloc(
CTRL_CMD_INFO,
NLM_F_DUMP
);
int ret = nl_send_auto(_nl, msg );
// test if fail
// wait for the ack
// read a reply
This code is for Aho-Corasick algorithm which i have refereed from here
I understood this code up to if block of push_links method but i didn't get the use or requirement for the else part of the same method.
More specifically first method is used for the construction of trie. The remaining work is done by second method i.e linking the node to their longest proper suffix which are prefix of some pattern also. This is carried out by the If block then what is the need of else part.
Please help me in this.
const int MAXN = 404, MOD = 1e9 + 7, sigma = 26;
int term[MAXN], len[MAXN], to[MAXN][sigma], link[MAXN], sz = 1;
// this method is for constructing trie
void add_str(string s)
{
// here cur denotes current node
int cur = 0;
// this for loop adds string to trie character by character
for(auto c: s)
{
if(!to[cur][c - 'a'])
{
//here two nodes or characters are linked using transition
//array "to"
to[cur][c - 'a'] = sz++;
len[to[cur][c - 'a']] = len[cur] + 1;
}
// for updating the current node
cur = to[cur][c - 'a'];
}
//for marking the leaf nodes or terminals
term[cur] = cur;
}
void push_links()
{
//here queue is used for breadth first search of the trie
int que[sz];
int st = 0, fi = 1;
//very first node is enqueued
que[0] = 0;
while(st < fi)
{
// here nodes in the queue are dequeued
int V = que[st++];
// link[] array contains the suffix links.
int U = link[V];
if(!term[V]) term[V] = term[U];
// here links for the other nodes are find out using assumption that the
// link for the parent node is defined
for(int c = 0; c < sigma; c++)
// this if condition ensures that transition is possible to the next node
// for input 'c'
if(to[V][c])
{
// for the possible transitions link to the reached node is assigned over
// here which is nothing but transition on input 'c' from the link of the
// current node
link[to[V][c]] = V ? to[U][c] : 0;
que[fi++] = to[V][c];
}
else
{
to[V][c] = to[U][c];
}
}
}
IMO you don't need the else-condition. If there is no children either it's already a link or nothing.
There are some variations of Aho-Corasick algorithm.
Base algorithm assumes that if edge from current node (cur) over symbol (c) is missing, then you go via suffix links to the first node that has edge over c (you make move via this edge).
But your way over suffix links is the same (from the same cur and c), because you don't change automaton while searching. So you can cache it (save result of
// start from node
while (parent of node doesn't have an edge over c) {
node = parent
}
// set trie position
node = to[node][c]
// go to next character
in to[node][c]. So next time you won't do this again. And it transfrom automaton from non-deterministic into deterministic state machine (you don't have to use link array after pushing, you can use only to array).
There are some problems with this implementation. First, you can get an index of string you found (you don't save it). Also, len array isn't used anywhere.
For
means, this algorithm is just checking the existence of the character in the current node link using "link[to[V][c]] = V ? to[U][c] : 0;". should not it verify in the parents link also?
Yes, it's ok, because if to[U][c] is 0, then there are no edges via c from all chain U->suffix_parent->suffix parent of suffix_parent ... -> root = 0. So you should set to[V][c] to zero.
I want to transfer data A1A2A3A4. From internal memory of ATxmega128A1 via SPI master to slave form into two seperate DAC converters such that DAC1 should have A1A3 and DAC2 with A2A4.
How can I write a code in AVR
// Transfer data from internal memory via SPI from Master to single Slave
if ( (SWITCHPORTL.IN & PIN2_bm) == 0 )
{
flip = false;
j = 0;
{
// Switch on LED 2
LEDPORT.OUTSET = PIN2_bm;
// Switch on LED 3
LEDPORT.OUTSET = PIN3_bm;
}
while (j < NUM_BYTES)
{
if (flip == false)
{
// Set slave select line low (active) for Port C
PORTC.OUTCLR = PIN4_bm;
}
// Give the data to the data register of the Master
SPIC.DATA = __far_mem_read(j+SDRAM_ADDR);
if (flip == true)
{
_delay_us(0.7); // wait for the 2nd 8-bit-block to be send -> delay 0.7us
// Set slave select line high (inactive)
PORTC.OUTSET = PIN4_bm;
_delay_us(1.9); // delay to adjust to sampling frequency 100 kHz -> 6.9us 200kHz -> 1.9us
}
flip = !flip;
j++;
}
}
Your general approach is right, but why do you not use SPIF flag of SPSR register? This will remove need of such precise _delay_us(0.7).
Also, looks like you forget to assert second chip select line.
So, general approach should be like following:
Read even byte (A1)
Assert slave select for first DAC.
Write data byte to SPIC.DATA
Loop while bit SPIF of SPSR == 0
Read from SPIC.DATA to clear SPIF bit.
Deassert slave select for first DAC
Read odd byte (A2)
Assert slave select for second DAC
Repeat steps 3-5
Repeat from beginning
Also, it is good idea to crate function that handles data write over SPI.
I want to implement a stack (push and pop operations) using a BST.
During post order traversal in a BST, root is placed at the top in the stack, while traversing iteratively.
So, does that mean I have to insert and delete elements from the root or something else?
int num=1;
struct node
{
int flag;
int val;
node *left,*right,*parent;
};
node* tree::InorderTraversalusingInBuiltstack()
{
stack<node *> p;
node *current=root;
while(!p.empty()|| current!=NULL)
{
while(current!=NULL)
{
p.push(current);
current=current->left;
}
current=p.top();
if(current->flag==num)
{
return current;
}
p.pop();
current=current->right;
}
}
void tree::StackUsingBST()
{
node *q;
while(root!=NULL)
{
num--;
q=InorderTraversalusingInBuiltqueue();
node *a=q->parent;
if(a!=NULL)
{
if(a->left==q)
a->left=NULL;
else
a->right=NULL;
q->parent=NULL;
delete q;
disp();
cout<<endl;
}
else
{
delete q;
root=NULL;
}
}
}
Here my approach is that i modified my data structure a bit, by using a flag variable
as a global variable;
suppose first i insert 8 then its corresponding flag value is 1
then insert 12 its flag value=2
then insert 3 its flag value=3
now inorder to use BST as a stack I have to delete the element which has been inserted last , and according to my algo having highest flag value.
Also note that the last element inserted will not have any child so its deletion is quite easy.
In order to find the highest flag value available with the nodes, I did a inordertraversal using stack which is better than its recursive traversal.
After finding that node corresponding to highest flag value ,I delete that node.
this process is repeated until root=NULL.