Code Warrior Assembly code - codewarrior

Question

I need some advice with a small program for school. If you could just point me in the right direction I would really appreciate it. I am using CodeWarrior coding in assembly language for the TWR-S12G128 Processor Module. My goal is to get the LEDs turn on and off with a delay of 1 second. Here is what my code looks like:
LDS #$4000 ; Initializing SP
LDAA #$FF
STAA DDRA ; Defines Port A as output
Back LDAA #$FF
STAA PORTA ; Turning all LEDs ON
JSR Delay
LDAA #$00
STAA PORTA ; Turning all LEDs OFF
JSR Delay
BSR Back
Delay PSHX ; 2-clock cycle
PSHY ; 2
LDY #20 ; 2-clock cycle
LOOP1 LDX #$FFFF ; 2
LOOP2 DEX ; 1-clock cycle
NOP ; 1-clock cycle
BNE LOOP2 ; 3-clock cycles/last cycle is 1
DEY ; 1
BNE $FF ; 3-clock cycles/last cycle is 1
PULY LOOP1 ; 3-clock cycle
PULX ; 3-clock cycle
RTS ; 5-clock cycle
There error that I am getting is :
Error : A2400: End of Line expected
main.asm line 58
Project: Project_4.mcp, Target: Standard, Source File: main.asm
Error : Compile failed
Project: Project_4.mcp, Target: Standard, Source File: main.asm

Answer 1

I don't know a great deal about the Freescale architecture but it's very unusual for any architecture to combine a pull instruction with a label.
The bne $ff is also unusual since that does normally specify a label.
I would be thinking that those two instructions should be more along the lines of:
bne loop1
puly
That makes more sense in that the pull instruction loses the label and the nested loops are properly constructed.

Answer 2

The $FF on the BNE line is not proper. I think it's a typo. I just worked this out with my professor a few hours ago. Here is the code that will give you the 1 second delay and continuously cycle the 4 LEDs on and off:
ABSENTRY Entry ; Application entry point
RAMStart EQU $2000
ROMStart EQU $C000
ORG RAMStart
; Insert here your data definition.
PTT EQU $240
DDRT EQU $242
; code section
ORG ROMStart
Entry:
_Startup:
LDS #$4000
Back LDAA #$FF
STAA DDRT
LDAA #$FF
STAA PTT
JSR Delay
LDAA #$00
STAA PTT
JSR Delay
BSR Back
Delay PSHX ; 2-clock cycle
PSHY ; 2
LDY #20 ; 2-clock cycle
LOOP1 LDX #$FFFF ; 2
LOOP2 DEX ; 1-clock cycle
NOP ; 1-clock cycle
BNE LOOP2 ; 3-clock cycles/last cycle is 1
DEY ; 1
BNE LOOP1 ; 3-clock cycles/last cycle is 1
PULY ; 3-clock cycle
PULX ; 3-clock cycle
RTS ; 5-clock cycle
ORG $FFFE
DC.W Entry ; Reset Vector
If someone would be so kind as to help me with the math. I get the 65,535 * 20 for the loops, but with the 6.25MHz clock, I end up getting .209 secs as the final amount for the delay, but I know it's suppose to be 1 sec. What am I not seeing?