makefile, size of an executable, static/dynamic - dynamic

I have a makefile, for a C project with 2 sub-C-files and I can create two exe, one static and one dynamic.
But the static is lighter in space than the dynamic!
The programs can be launched and seems to be the sames
Is it normal?
Thank you very much, I have an exam in 2 days and I hope I will fix that problem :)
Simon
CC = gcc
CFLAGS = -Wall
CFLAGS2 = -shared
CFLAGS3 = -fPIC
LIB_U_CAM_TTL = -l_projet_vision_u_cam_ttl
LIB_SERIAL_LINUX = -l_projet_vision_serial_linux
CHEMIN = -L/usr/local/lib
lib_projet_vision_serial_linux.so: serial_linux.o
$(CC) $(CFLAGS2) $^ -o $#
lib_projet_vision_u_cam_ttl.so: u_cam_ttl.o
$(CC) $(CFLAGS2) $^ -o $#
lib_projet_vision_serial_linux.a : serial_linux.o
ar -rv $# $^
lib_projet_vision_u_cam_ttl.a : u_cam_ttl.o
ar -rv $# $^
projet_vision_dynamic: main_vision.c install
$(CC) $(CFLAGS3) $^ $(CHEMIN) $(LIB_SERIAL_LINUX) $(LIB_U_CAM_TTL) -o $#
projet_vision_static: main_vision.c install
$(CC) $^ $(CHEMIN) $(LIB_SERIAL_LINUX) $(LIB_U_CAM_TTL) -o $#
%.o : %.c
$(CC) $(CFLAGS) -c $< -o $#
install: lib_projet_vision_serial_linux.so lib_projet_vision_serial_linux.a lib_projet_vision_u_cam_ttl.so lib_projet_vision_u_cam_ttl.a
sudo cp -f *.h /usr/local/include/
sudo cp -f *.so /usr/local/lib/
sudo cp -f *.a /usr/local/lib/
sudo cp projet_vision_dynamic /usr/bin/
sudo cp projet_vision_static /usr/bin/
sudo ldconfig
uninstall: clean
sudo rm -f /usr/local/include/serial_linux.h
sudo rm -f /usr/local/include/u_cam_ttl.h
sudo rm -f /usr/local/lib/lib_projet_vision_serial_linux.so
sudo rm -f /usr/local/lib/lib_projet_vision_u_cam_ttl.so
sudo rm -f /usr/local/lib/lib_projet_vision_u_cam_ttl.a
sudo rm -f /usr/local/lib/lib_projet_vison_serial_linux.a
sudo ldconfig
clean:
rm -f *.o *~ *.so *.a
rm -f projet_vision_static projet_vision_dynamic

Related

Can I build my PC file (Oracle Pro*c) conditionally inside of my application's make file?

I'm attempting to combine my makefiles so I can simply build once and it will precompile the pc file completely before continuing to build the application. This should be possible but for the life of me I cannot figure it out. Here is my makefile (for redhat 7).
COMPILEDATE = $(shell date)
COMPILE=g++ -std=c++11 -Wall -Wuninitialized -g
OSTYPE = $(shell uname)
LIBDIR=../../lib/
INC=../../include/
FILES=myProcess
OBJS= myProcess.o \
sqlStuff.o
O8P=$(ORACLE_HOME)
O8P=/u01/app/oracle/11.2.0/client_1
ORACLE_HOME=/u01/app/oracle/11.2.0/client_1
PROC_LINES=proc lines=yes code=ANSI_C iname=sqlStuff.pc parse=partial iname=sqlStuff include=. include=$(ORACLE_HOME)/precomp/public include=$(ORACLE_HOME)/rdbms/public include=$(ORACLE_HOME)/rdbms/demo include=$(ORACLE_HOME)/plsql/public include=$(ORACLE_HOME)/network/public
all: $(FILES)
compileInfo.o : FORCE
$(COMPILE) -c compileInfo.cpp -o $# -I$(INC) -DCDATE="\"$(COMPILEDATE)\"" -DBUILD="\"$(LSWBUILD)\""
FORCE :
%.o : %.cpp $(INC)myProcess.h
$(COMPILE) -c $< -o $# -I$(INC) -DCDATE="\"$(COMPILEDATE)\""
sqlStuff.o : sqlStuff.c
gcc -g -Wall -O -c -lclntsh -I. -I$(ORACLE_HOME)/precomp/public -I$(ORACLE_HOME)/rdbms/public -I$(ORACLE_HOME)/rdbms/demo -I$(ORACLE_HOME)/plsql/lib -I$(ORACLE_HOME)/network/lib
sqlStuff.c : sqlStuff.pc
$(PROC_LINES)
myProcess: $(OBJS) $(LIBDIR)libbase.a $(INC)myProcess.h sqlStuff.o
$(COMPILE) -o myProcess$(OBJS) -L$(LIBDIR) -lbase
clean:
rm -f $(FILES)
rm -f sqlStuff
rm -f sqlStuff.c
rm -f sqlStuff.lis
rm -f $(OBJS)
rm -f core
rm -f *.out
rm -f *.log
rm -f *.err
My fault, I didn't explain what the issue was:
I'm compiling in netbeans using this build command: ${MAKE} -f Makefile. The error is PCC-S-02015, unable to open include file on my object that is not being precompiled, sqlStuff.o
Looking at the gcc command under sqlStuff.o : sqlStuff.c, it looks to me that there should be a -o sqlStuff.o flag to tell gcc that the output should be written to sqlStuff.o instead of the default, which is a.out.
Best of luck.

Makefile rule using the automatic variable $^ without dependencies

I learnt from the GNU Make manual that the sign $^ is an automatic variable which represents the names of all the prerequisites. However I fell upon a makefile like this one:
SVR_OBJECT_FILES = server.o\
server_func.o
CLT_OBJECT_FILES = client.o
CFLAGS = -Wall -Werror -W
CC = gcc
all: client/client server/serveur
client/client: $(CLT_OBJECT_FILES)
server/serveur: $(SVR_OBJECT_FILES)
client/client server/serveur:
#mkdir -p $(dir $#)
$(CC) $(CFLAGS) $^ -o $#
%.o: %.c
$(CC) -c $<
clean:
rm -f client/client server/serveur *.o
Which works fine so my question is :
How can the command below can link the right object files while the $^ variable is refering no preprerequisites at all. (the rule has no prerequisites)
$(CC) $(CFLAGS) $^ -o $#
$^ contains all the prerequisites of the target, not just the ones that are mentioned with the rule itself. The same file can appear as a target several times in rules with no commands:
sometarget: dependency1
…
sometarget: dependency2
assemble -o $# $^
…
sometarget: dependency3
The dependencies of sometarget are dependency1, dependency2 and dependency3, and when the assemble command is invoked by make sometarget, it will receive all three as arguments.
Here, $^ will contain all $(CLT_OBJECT_FILES) or $(SRV_OBJECT_FILES) depending on which target the command is executed for.

gcc Makefile: Variable Substitution error with %

My make file has worked, up until I tried some variable substitution. %.o is not recognized.
I get make: * No rule to make target `%.o', needed by `parser'. Stop.
CC=gcc
CFLAGS=-ansi -pedantic -Wall -ggdb3
PROJECT=project.c project.h
PARSER=parser.c parser.h
OBJ=project.o parser.o
#CFILE=project.c parser.c
#1 no problem
#parser: project.o parser.o
# $(CC) $(CFLAGS) -o $# $^
#2 no problem
#parser: $(OBJ)
# $(CC) $(CFLAGS) -o $# $^
#3 this fails
parser: %.o
$(CC) $(CFLAGS) -o $# $^
#parser: project.o parser.o
# gcc -ansi -pedantic -Wall -ggdb -o parser project.o parser.o
project.o: $(PROJECT)
$(CC) $(CFLAGS) -c $^
parser.o: $(PARSER)
$(CC) $(CFLAGS) -c $^
clean:
rm -f $(OBJ) parser
You're not creating a pattern rule, since there is no % in the target name. As a result the % has no special meaning in the list of dependencies. It's seen as a literal part of a file name; you can't use it as a regular wildcard.

Prepending a path on make

In my makefile I have an object variable. I need to prepend obj/ to every .o file. How would I do this?
CC=g++
CFLAGS=-C -Wall
LDFLAGS=-lsqlite3 -lpthread -ldl
SOURCES=main.cpp Database.cpp actionInit.cpp TileSet.cpp Player.cpp
OBJECTS=$(SOURCES:.cpp=.o)
EXECUTABLE=mahjong-counter
all: bin $(OBJECTS) $(EXECUTABLE)
bin:
mkdir -p bin
%.o: %.cpp
$(CC) $(LDFLAGS) $< -c -o $#
$(EXECUTABLE): $(OBJECTS)
$(CC) $(LDFLAGS) $(OBJECTS) -o $(EXECUTABLE)
clean:
rm $(OBJECTS)
You want CXX, not CC. CC is for C compiler, not the C++ compiler
In any case, I believe the following should work:
CXX=g++
CXXFLAGS=-C -Wall
LDFLAGS=-lsqlite3 -lpthread -ldl
OBJ_DIR = obj
BIN_DIR = bin
EXECUTABLE=mahjong-counter
SOURCES= main.cpp Database.cpp actionInit.cpp TileSet.cpp Player.cpp
OBJECTS= $(SOURCES:%.cpp=$(OBJ_DIR)/%.o)
all: dirs $(OBJECTS) $(EXECUTABLE)
$(EXECUTABLE): $(OBJECTS)
$(CC) $(LDFLAGS) $(OBJECTS) -o $(EXECUTABLE)
$(OBJ_DIR)/%.o: %.cpp
$(CXX) $(CXXFLAGS) $< -o $#
dirs:
mkdir -p $(BIN_DIR)
mkdir -p $(OBJ_DIR)
.PHONY: dirs all
You could use more expressive version of substitution you employed when assigning OBJECTS
OBJECTS=$(SOURCES:%.cpp=obj/%.o)
or use a standard text transformation function
OBJECTS=$(addprefix obj/,$(SOURCES:.cpp=.o))

How to write a shell script to compile multiple embedded sql in C files (.sqc)?

I have written 3 .sqc files i.e. embedded sql in host language C. I need to make a (Unix) shell script to simply compile all 3 sqc files in a row. How can I do that? Right now, I can individually run each .sqc file using a Makefile that basically converts the .sqc file to a c file and then compiles it. Can I make 3 individual Makefiles and run all of them through a shell script? If so, then how? Can I make one Makefile that can compile all 3 .sqc independently and compile them thereafter through a shell script? If so, then how? Any other options?
Here is the Makefile that can only compile a single .sqc file:
NAME=sample
DB2PATH = /sqllib
CC=gcc
CFLAGS=-I$(DB2PATH)/include
LIBS=-L$(DB2PATH)/lib -R$(DB2PATH)/lib -ldb2
all: $(NAME)
$(NAME): $(NAME).sqc util.o
db2 connect to sampleDB
db2 prep $(NAME).sqc bindfile
db2 bind $(NAME).bnd
db2 connect reset
$(CC) $(CFLAGS) -c $(NAME).c
$(CC) $(CFLAGS) -o $(NAME) $(NAME).o util.o $(LIBS)
clean:
rm -f $(NAME) $(NAME).c $(NAME).o $(NAME).bnd
util.o : util.c
$(CC) -c util.c $(CFLAGS)
A possible (Unix) shell script and Makefile example would suffice to help.
Thank you.
This Makefile should do all three in one step, just type "make". Note that you'll have to change the second line to reflect the names of your real .sqc files.
Also note that I'm not familiar with sqc and I haven't tested this, I'm just working from your Makefile.
# THIS IS THE ONLY LINE YOU'LL HAVE TO CHANGE:
NAMES = file1 file2 file3
DB2PATH = /sqllib
CC=gcc
CFLAGS=-I$(DB2PATH)/include
LIBS=-L$(DB2PATH)/lib -R$(DB2PATH)/lib -ldb2
all: $(NAMES)
# This will convert .sqc into .c
%.c: %.sqc
db2 connect to sampleDB
db2 prep $< bindfile
db2 bind $*.bnd
db2 connect reset
# This will compile .c into .o, whether it's fileN.c or util.c
%.o: %.c
$(CC) $(CFLAGS) -c $< -o $#
# This will link fileN.o and util.o into fileN
$(NAMES): % : %.o util.o
$(CC) $(CFLAGS) -o $# $^ $(LIBS)
# This is just to assure Make that that isn't really a file called "clean"
.PHONY: clean
clean:
rm -f $(NAMES) $(NAMES:=.c) $(NAMES:=.o) $(NAMES:=.bnd)
DB2PATH = /sqllib
CC=gcc
CFLAGS=-I$(DB2PATH)/include
LIBS=-L$(DB2PATH)/lib -R$(DB2PATH)/lib -ldb2
all: $(NAME)
$(NAME): $(NAME).sqc util.o
db2 connect to sampleDB
db2 prep $(NAME).sqc bindfile
db2 bind $(NAME).bnd
db2 connect reset
$(CC) $(CFLAGS) -c $(NAME).c
$(CC) $(CFLAGS) -o $(NAME) $(NAME).o util.o $(LIBS)
clean:
rm -f $(NAME) $(NAME).c $(NAME).o $(NAME).bnd
util.o : util.c
$(CC) -c util.c $(CFLAGS)
suppose you have three files: file1.sqc file2.sqc file3.sqc, and your makefile is saved as mksqc.mk
Script:
make -f mksqc.mk NAME=file1
make -f mksqc.mk NAME=file2
make -f mksqc.mk NAME=file3