I have a Makefile with this content
$ cat Makefile
all: locality
locality: src/locality.o
g++ src/locality.o -o locality
locality.o: src/locality.cpp
g++ -O3 -c src/locality.cpp
clean:
rm -rf src/*.o locality
However when I run make, I see some slightly different output!
$ make clean
rm -rf src/*.o locality
$ make
g++ -c -o src/locality.o src/locality.cpp
g++ src/locality.o -o locality
So where is -O3??
You tripped over a built-in rule in GNU make, namely %.o: %.c. Use $CFLAGS instead.
CFLAGS=-O3
all: locality
locality: src/locality.o
g++ src/locality.o -o locality
clean:
rm -rf src/*.o locality
Make is using an implicit rule to create src/locality.o because you have no rule for it (you only have a rule for locality.o in the current directory, not in src.
This is what you get for violating one of Paul's rules of Makefiles:
Every non-.PHONY rule must update a file with the exact name of its target.
To do that, you should use $# in your rule to designate the target file.
Related
I am kinda rookie in makefile field but trying to write makefile that would go in two modes: normal mode make outputing executable file called say bingo depending on some files and a mode make debug outputing executable file called bingo.debug that shall be compiled with debug option. I'm trying to use target variable with the following result:
PROGRAM = bingo
SUFIX = .debug
CC = gcc
CFLAGS = -Wall -O2
DEBUG = -g -D DEBUG
all: $(PROGRAM)
debug: CFLAGS += $(DEBUG)
debug: PROGRAM += $(SUFIX)
debug: all
file1.o: file1.c file1.h
$(CC) -c $(CFLAGS) -o $# $<
file2.o: file2.c file2.h
$(CC) -c $(CFLAGS) -o $# $<
$(PROGRAM).o: $(PROGRAM).c
$(CC) -c $(CFLAGS) -o $# $<
$(PROGRAM): file1.o file2.o ($PROGRAM).o
$(CC) -o $# $^
.PHONY: all clean
clean:
rm -rf $(PROGRAM) *.o
It looks like make debug correctly compiles the file with debug flags but it does not change the file name (i.e. both modes outputs the same bingo file). Any help much appriciated!
You cannot use target-specific variables in targets. The documentation is very clear that they are available only in recipes.
In general it's problematic to do things this way, because make has no idea which objects were built with debug and which weren't. If you forget to do a complete clean and/or run make the wrong way then you'll get a mix of different object files: some compiled with debug and some not.
Instead, you should put your debug object files in a different directory from your non-debug object files so you don't have to worry about that.
I'm attempting to combine my makefiles so I can simply build once and it will precompile the pc file completely before continuing to build the application. This should be possible but for the life of me I cannot figure it out. Here is my makefile (for redhat 7).
COMPILEDATE = $(shell date)
COMPILE=g++ -std=c++11 -Wall -Wuninitialized -g
OSTYPE = $(shell uname)
LIBDIR=../../lib/
INC=../../include/
FILES=myProcess
OBJS= myProcess.o \
sqlStuff.o
O8P=$(ORACLE_HOME)
O8P=/u01/app/oracle/11.2.0/client_1
ORACLE_HOME=/u01/app/oracle/11.2.0/client_1
PROC_LINES=proc lines=yes code=ANSI_C iname=sqlStuff.pc parse=partial iname=sqlStuff include=. include=$(ORACLE_HOME)/precomp/public include=$(ORACLE_HOME)/rdbms/public include=$(ORACLE_HOME)/rdbms/demo include=$(ORACLE_HOME)/plsql/public include=$(ORACLE_HOME)/network/public
all: $(FILES)
compileInfo.o : FORCE
$(COMPILE) -c compileInfo.cpp -o $# -I$(INC) -DCDATE="\"$(COMPILEDATE)\"" -DBUILD="\"$(LSWBUILD)\""
FORCE :
%.o : %.cpp $(INC)myProcess.h
$(COMPILE) -c $< -o $# -I$(INC) -DCDATE="\"$(COMPILEDATE)\""
sqlStuff.o : sqlStuff.c
gcc -g -Wall -O -c -lclntsh -I. -I$(ORACLE_HOME)/precomp/public -I$(ORACLE_HOME)/rdbms/public -I$(ORACLE_HOME)/rdbms/demo -I$(ORACLE_HOME)/plsql/lib -I$(ORACLE_HOME)/network/lib
sqlStuff.c : sqlStuff.pc
$(PROC_LINES)
myProcess: $(OBJS) $(LIBDIR)libbase.a $(INC)myProcess.h sqlStuff.o
$(COMPILE) -o myProcess$(OBJS) -L$(LIBDIR) -lbase
clean:
rm -f $(FILES)
rm -f sqlStuff
rm -f sqlStuff.c
rm -f sqlStuff.lis
rm -f $(OBJS)
rm -f core
rm -f *.out
rm -f *.log
rm -f *.err
My fault, I didn't explain what the issue was:
I'm compiling in netbeans using this build command: ${MAKE} -f Makefile. The error is PCC-S-02015, unable to open include file on my object that is not being precompiled, sqlStuff.o
Looking at the gcc command under sqlStuff.o : sqlStuff.c, it looks to me that there should be a -o sqlStuff.o flag to tell gcc that the output should be written to sqlStuff.o instead of the default, which is a.out.
Best of luck.
I learnt from the GNU Make manual that the sign $^ is an automatic variable which represents the names of all the prerequisites. However I fell upon a makefile like this one:
SVR_OBJECT_FILES = server.o\
server_func.o
CLT_OBJECT_FILES = client.o
CFLAGS = -Wall -Werror -W
CC = gcc
all: client/client server/serveur
client/client: $(CLT_OBJECT_FILES)
server/serveur: $(SVR_OBJECT_FILES)
client/client server/serveur:
#mkdir -p $(dir $#)
$(CC) $(CFLAGS) $^ -o $#
%.o: %.c
$(CC) -c $<
clean:
rm -f client/client server/serveur *.o
Which works fine so my question is :
How can the command below can link the right object files while the $^ variable is refering no preprerequisites at all. (the rule has no prerequisites)
$(CC) $(CFLAGS) $^ -o $#
$^ contains all the prerequisites of the target, not just the ones that are mentioned with the rule itself. The same file can appear as a target several times in rules with no commands:
sometarget: dependency1
…
sometarget: dependency2
assemble -o $# $^
…
sometarget: dependency3
The dependencies of sometarget are dependency1, dependency2 and dependency3, and when the assemble command is invoked by make sometarget, it will receive all three as arguments.
Here, $^ will contain all $(CLT_OBJECT_FILES) or $(SRV_OBJECT_FILES) depending on which target the command is executed for.
I want my Makefile to be as simple as possible and still function. This is what it looks like.
load: load.cpp
g++ load.cpp -g -o load
list: list.cpp
g++ list.cpp -g -o list
It worked fine when there was only one entry. But when I added the second entry, it doesn't check to see if it's updated and needs to be recompiled, unless I specifically supply the name. How do I fix this?
Make only makes the first target automatically. So add a new first target that depends on both the others.
all: load list
load: load.cpp
g++ load.cpp -g -o load
list: list.cpp
g++ list.cpp -g -o list
Dave Hinton has shown how to get the Makefile to work. Here's how to make it simpler:
all: load list
%: %.cpp
g++ $< -g -o $#
When I run make on the following Makefile, when is the symbol table built, if it even is?
LEX = flex
YACC = yacc
CC = gcc
calcu: y.tab.o lex.yy.o
$(CC) -o calcu y.tab.o lex.yy.o -ly -lfl
y.tab.c y.tab.h: parser.y
$(YACC) -d parser.y
y.tab.o: y.tab.c parser.h
$(CC) -c y.tab.c
lex.yy.o: y.tab.h lex.yy.c
$(CC) -c lex.yy.c
lex.yy.c: calclexer.l parser.h
$(LEX) calclexer.l
clean:
rm *.o
rm *.c
rm calcu
make doesn't build symbol tables (obviously the compilers and linkers it invokes will have to do that!). I'll assume you're referring to whatever the resulting calcu binary does wrt its input, instead.
If any such thing as a "symbol table" is ever built by calcu, it will be by code you inserted into parser.y that gets moved over into yacc.tab.c; as to when, it will be during the course of a calcu run over whatever its input is -- incrementally, as each syntax production including "symbol-table building code" matches.