I have two packed arrays of signals and I need to create a property and associated assertion for that property that proves that the two arrays are identical under certain conditions. I am formally verifying and the tool cannot prove both full arrays in a single property, so I need to split it up into individual elements. So is there a way I can generate a properties for each element of the array using a loop? At the moment my code is very verbose and hard to navigate.
My code currently looks like this:
...
property bb_3_4_p;
#(posedge clk)
bb_seq
|=>
bb_exp [3][4] == bb_rtl [3][4] ;
endproperty
property bb_3_5_p;
#(posedge clk)
bb_seq
|=>
bb_exp [3][5] == bb_rtl [3][5] ;
endproperty
property bb_3_6_p;
#(posedge clk)
bb_seq
|=>
bb_exp [3][6] == bb_rtl [3][6] ;
endproperty
...
...
assert_bb_3_4: assert property (bb_3_4_p);
assert_bb_3_5: assert property (bb_3_5_p);
assert_bb_3_6: assert property (bb_3_6_p);
...
This is sort of how I'd like my code to look like:
for (int i = 0; i < 8; i++)
for (int j = 0; j < 8; j++)
begin
property bb_[i]_[j]_p;
#(posedge clk)
bb_seq
|=>
bb_exp [i][j] == bb_rtl [i][j] ;
endproperty
assert_bb_[i]_[j]: assert property (bb_[i]_[j]_p);
end
You might try declaring the property with ports so you can reuse it for multiple assertions. Then declare your assertions using a generate loop.
module
...
property prop1(signal1,signal2);
#(posedge clk)
bb_seq
|=>
signal1 == signal2 ;
endproperty
...
generate
for (genvar i = 0; i < 8; i++)
for (genvar j = 0; j < 8; j++)
begin : assert_array
assert property (prop1(bb_exp[i][j],bb_rtl[i][j]));
end
endgenerate
...
endmodule
You could also inline the property in the assertion:
module
...
generate
for (genvar i = 0; i < 8; i++)
for (genvar j = 0; j < 8; j++)
begin : assert_array
assert property (#(posedge clk) bb_seq |=> bb_exp[i][j] == bb_rtl[i][j]);
end
endgenerate
...
endmodule
You can also try the same thing with a macro.
/*Start of macro*/
`define bb_prop(Num1, Num2) \
property bb_``NUM1``_``NUM2``_p; \
#(posedge clk) \
bb_seq |=> bb_exp [``NUM1``` ][``NUM2``] == bb_rtl [``NUM1``` ][``NUM2``]; \
endproperty \
bb_prop_``NUM1``_``NUM2``_assert: assert property (bb_``NUM1``_``NUM2``_p)
/* End of macro*/
`bb_prop(3,4)
`bb_prop(3,5)
`bb_prop(3,6)
Related
In the following method, Dafny reports that the postcondition might not hold, even though I am quite sure that it does.
method toArrayConvert(s:seq<int>) returns (a:array<int>)
requires |s| > 0
ensures |s| == a.Length
ensures forall i :: 0 <= i < a.Length ==> s[i] == a[i] // This is the postcondition that might not hold.
{
a := new int[|s|];
var i:int := 0;
while i < |s|
decreases |s| - i
invariant 0 <= i <= |s|
{
a[i] := s[i];
i := i + 1;
}
return a; // A postcondition might not hold on this return path.
}
Indeed, the postcondition does always hold, but Dafny cannot tell!
That's because you're missing a loop invariant annotation such as
invariant forall j :: 0 <= j < i ==> s[j] == a[j]
After adding that line to the loop, the method verifies.
For more explanation about why Dafny sometimes reports errors on correct programs, see the (brand new) FAQ. For more about loop invariants, see the corresponding section in the rise4fun guide.
Instead of this task just toggling tb.stimulus.top.Ichip0.vbiash high and low ten times I would like to be able to call it passing in any signal tb.stimulus.top.Ichip0.vbiasl, tb.stimulus.top.Ichip0.vbiasx, or tb.stimulus.top.Ichip0.vbiasz and make them toggle as well. For example toggle_signal(tb.stimulus.top.Ichip0.vbiasl); Is it possible to do this. If so I would really appreciate an example of how I would accomplish this.
task toggle_signal;
begin
for (monpad_index=0; monpad_index < 10; monpad_index = monpad_index + 1)
begin
#1000;
force tb.stimulus.top.Ichip0.vbiash = 1'b1;
#1000;
force tb.stimulus.top.Ichip0.vbiash = 1'b1;
#1000;
end
end
You cannot pas the name of a single to a task. But you can create a macro to do this.
`define toggle_signal(sig) \
for (monpad_index=0; monpad_index < 10; monpad_index = monpad_index + 1) \
begin \
#1000 force tb.stimulus.top.Ichip0.sig = 1'b1; \
#1000 force tb.stimulus.top.Ichip0.sig = 1'b0; \
#1000; \
end
and then write
`toggle_signal(vbiash)
`toggle_signal(vbiasl)
If you are not afraid do dive into a little C programming, you could write your own PLI/VPI. I suggest checking out IEEE Std 1800-2012's sections on PLI/VPI (§ 36, 37, & 38). Your come may looks something like the following (Note, the code is a starting reference. I haven't tested it):
static int my_vpi_force_release_calltf(PLI_BYTE* user_data) {
vpiHandle sys, argv, signal;
p_vpi_value p_value;
int force_release;
force_release = (int) user_data;
sys = vpi_handle(vpiSysTfCall, 0);
argv = vpi_iterate(vipArgument, sys);
signal = vpi_handle_by_name(vpi_get_str(vpi_scan(argv), 0);
if (force_release != 0 ) {
vpi_get_value(vpi_scan(argv), p_value);
vpi_put_value(signal, p_value, 0, vpiForceFlag);
} else {
vpi_get_value(signal, p_value);
vpi_put_value(signal, p_value, 0, vpiReleaseFlag);
}
return 0;
}
void register_my_vpi_force_release()
{
s_vpi_systf_data data;
data.type = vpiSysTask;
data.calltf = my_vpi_force_release_calltf;
data.tfname = "$my_force";
data.user_data = (PLI_BYTE8 *) 1;
vpi_register_systf(&data);
data.tfname = "$my_release";
data.user_data = (PLI_BYTE8 *) 0;
vpi_register_systf(&data);
}
You can call your PLI/VPI tasks in verilog:
task toggle_signal( input [80*8-1:0] path_str );
integer index;
begin
for (index=0; index < 10; index = index + 1)
begin
#1000;
$my_force( path_str, 1'b1);
#1000;
$my_force( path_str, 1'b0 );
#1000;
end
$my_release( path_str );
end
endtask
...
initial begin
...
toggle_signal( "tb.stimulus.top.Ichip0.vbiash" );
...
end
If you don't want to write your own custom PLI/VPI, then I suggest enabling SystemVerilog and include UVM (the major simulators have UVM build in, or download it yourself). The UVM library has a build in method uvm_hdl_force/uvm_hdl_release.
Here you go. The following code passes a signal name as a parameter to a task then prints the signal name as a string. Tested in iverilog.
reg this_is_some_signal_name;
`define NAME(net) `"net`"
task print;
input reg [32*8] str;
begin
$display(">>> %0s", str);
end
endtask
initial begin
print(`NAME(this_is_some_signal_name));
$finish;
end
Outputs:
>>> this_is_some_signal_name
So I'm trying to instantiate a module within a module. The root module has output ports that drive the output pins and I want the inner module to drive those ports directly but I can't get it work anyway round.
/*
A root module for the 005_135-scanner_mainboard_revA_sch-pcb. Can be used as a test bench for testing peripheral devices but has been designed to be the master root module for the final code.
All IO is included and reset pins on peripheral devices driven active reset with data lines driven to an appropriate value (located in the ‘initial block’).
George Waller. 09/08/15.
*/
module root_module( ft_reset, ft_usb_prsnt, ft_bus_pwrsav, ft_bus_oe, ft_bus_clkout, ft_bus_siwu, ft_bus_wr, ft_bus_rd, ft_bus_rxf, ft_bus_txe, ft_bus_d,
mtr_fault, mtr_config, mtr_m1, mtr_m0, mtr_rst, mtr_out_en, mtr_step, mtr_dir,
ccd_driver_oe, ccd_p1, ccd_p2, ccd_cp, ccd_rs, ccd_sh,
dac1_sdin, dac1_sclk, dac1_sync, dac2_sdin, dac2_sclk, dac2_sync,
adc_pwrdn, adc_encode, adc_d,
fpga_reset,
clk,
gpio,
led_ctrl,
leds);
//Input declarations
input wire ft_usb_prsnt, ft_bus_clkout, ft_bus_rxf, ft_bus_txe,
mtr_fault,
fpga_reset,
clk;
input wire [7:0] adc_d;
//Output declarations
output reg ft_reset, ft_bus_pwrsav, ft_bus_oe, ft_bus_siwu, ft_bus_wr, ft_bus_rd,
mtr_config, mtr_m1, mtr_m0, mtr_rst, mtr_out_en, mtr_step, mtr_dir,
ccd_driver_oe, ccd_p1, ccd_p2, ccd_cp, ccd_rs, ccd_sh,
adc_pwrdn, adc_encode,
led_ctrl;
output reg dac1_sdin, dac1_sclk, dac1_sync, dac2_sdin, dac2_sclk, dac2_sync;
output reg [7:0] leds;
//Input output declarations.
inout reg [7:0] ft_bus_d;
inout reg [16:0] gpio;
//Variables go here
integer count, count1, state, pixel_n, line_n, t_int;
integer data[8];
reg en;
//Initial values on start up.
initial
begin
//IO initial setup values.
ft_reset = 1; ft_bus_pwrsav = 1; ft_bus_oe = 1; ft_bus_siwu = 0; ft_bus_wr = 1; ft_bus_rd = 1; //NEED TO APPLY REAL VAULES!!!
mtr_config = 1; mtr_m1 = 1; mtr_m0 = 1; mtr_rst = 1; mtr_out_en = 1; mtr_step = 0; mtr_dir = 0;
ccd_driver_oe = 1; ccd_p1 = 0; ccd_p2 = 0; ccd_cp = 0; ccd_rs = 0; ccd_sh = 0;
dac1_sdin = 0; dac1_sclk = 0; dac1_sync = 0; dac2_sdin = 0; dac2_sclk = 0; dac2_sync = 0;
adc_pwrdn = 0; adc_encode = 0;
led_ctrl = 0;
leds = 0;
gpio = 0;
ft_bus_d = 0;
//Variables setup values.
count = 0;
count1 = 0;
state = 0;
pixel_n = 0;
line_n = 0;
t_int = 10000; //t_int = integration time. integration time (seconds) = t_int * 10x10^-9.
end //End initial
//Some other code goes here.
always #(posedge ft_bus_clkout)
begin
if(count == 50000000)
begin
en <= 1;
count = 0;
end
else
begin
en <= 0;
count = count + 1;
end
end //End always
AD5601_module AD5601(.en(en), .clk(clk), .data(127),.sdout(dac1_sdin),
.sclk(dac1_sclk), .sync(dac1_sync));
endmodule //End module.
And the inner module:
module AD5601_module(en, clk, data, sdout, sclk, sync);
input wire clk;
input wire en;
input wire [7:0] data;
output reg sdout, sclk, sync;
integer sclk_count;
integer data_state;
integer delay_counter;
integer pd[2];
initial
begin
sclk_count = 0;
data_state = 99;
delay_counter = 0;
pd[0] = 0;
pd[1] = 0;
sdout = 0;
sclk = 0;
sync = 1;
end
always # (posedge en)
begin
if(data_state == 99)data_state <= 0;
end
always # (posedge clk)
begin
if(sclk_count == 49)
begin
sclk_count = 0;
sclk = ~sclk;
end
else sclk_count = sclk_count + 1;
end
always # (posedge sclk)
begin
case(data_state)
0: begin
sync = 0;
sdout <= pd[1];
data_state <= 1;
end
1: begin
sdout <= pd[0];
data_state <= 2;
end
2: begin
sdout <= data[7];
data_state <= 3;
end
3: begin
sdout <= data[6];
data_state <= 4;
end
4: begin
sdout <= data[5];
data_state <= 5;
end
5: begin
sdout <= data[4];
data_state <= 6;
end
6: begin
sdout <= data[3];
data_state <= 7;
end
7: begin
sdout <= data[2];
data_state <= 8;
end
8: begin
sdout <= data[1];
data_state <= 9;
end
10:begin
sdout <= 0;
if(delay_counter == 6)
begin
data_state <= 99;
delay_counter <= 0;
sync = 1;
end
else delay_counter = delay_counter + 1;
end
endcase
end
endmodule
So with the code as is I get the error
'output or inout port should be connected to a structural net
expression'
.
If I change the outputs in the root module or the inner module to wire I get the error 'the expression on the left hand side should be of a variable type'.
So at this point I have no idea how you nest outputs! Some help would be appreciated!
Thanks
inout ports should be a net type (wire or tri) and not a reg. A reg does not have conflict resolution (when there are two or more active driver). An inout should not be assigned in a procedural block (e.g. always-block, initial-block). It should be a simple assign statement as below. The designer must ensure there is only on active driver on the IO at any point.
assign io_port_name = driver_enable ? io_out_value : 'bz; // io_out_value should be a flop
An output should only be declared an output reg if it is assigned in a procedural block (e.g. always-block, initial-block) within the current module. All other outputs should be output or output wire (these identifiers are synonymous; the former is implicit while the latter is explicit). An should only be assigned within one always. FPGAs allow initial blocks, ASIC/IC does not.
If SystemVerilog is enabled, replace output reg with output logic. logic can be used for flops and single directional nets. logic is not recommended for inout; logic like reg does not have conflict resolution.
The arrays integer data[8]; and integer pd[2]; are SystemVerilog syntax and not compatible with Verilog. Either enable SystemVerilog or change to integer data[0:7]; and integer pd[0:1];
SystemVerilog can be enabled per file by changing the file extension from .v to .sv; recommended. Simulators/synthesizers typically have a switch to force all Verilog to be treated as SystemVerilog; not recommended, refer to the simulator/synthesizer manual if desired to go this route.
I seem to have some issues anytime I try anything with I/O for verilog. Modelsim either throws function not supported for certain functions or does nothing at all. I simply need to read a file character by character and send each bit through the port. Can anyone assist
module readFile(clk,reset,dEnable,dataOut,done);
parameter size = 4;
//to Comply with S-block rules which is a 4x4 array will multiply by
// size so row is the number of size bits wide
parameter bits = 8*size;
input clk,reset,dEnable;
output dataOut,done;
wire [1:0] dEnable;
reg dataOut,done;
reg [7:0] addr;
integer file;
reg [31:0] c;
reg eof;
always#(posedge clk)
begin
if(file == 0 && dEnable == 2'b10)begin
file = $fopen("test.kyle");
end
end
always#(posedge clk) begin
if(addr>=32 || done==1'b1)begin
c <= $fgetc(file);
// c <= $getc();
eof <= $feof(file);
addr <= 0;
end
end
always#(posedge clk)
begin
if(dEnable == 2'b10)begin
if($feof(file))
done <= 1'b1;
else
addr <= addr+1;
end
end
//done this way because blocking statements should not really be used
always#(addr)
begin:Access_Data
if(reset == 1'b0) begin
dataOut <= 1'bx;
file <= 0;
end
else if(addr<32)
dataOut <= c[31-addr];
end
endmodule
I would suggest reading the entire file at one time into an array, and then iterate over the array to output the values.
Here is a snippet of how to read bytes from a file into a SystemVerilog queue. If you need to stick to plain old Verilog you can do the same thing with a regular array.
reg [8:0] c;
byte q[$];
int i;
// Read file a char at a time
file = $fopen("filename", "r");
c = $fgetc(file);
while (c != 'h1ff) begin
q.push_back(c);
$display("Got char [%0d] 0x%0h", i++, c);
c = $fgetc(file);
end
Note that c is defined as a 9-bit reg. The reason for is that $fgetc will return -1 when it reaches the end of the file. In order to differentiate between EOF and a valid 0xFF you need this extra bit.
I'm not familiar with $feof and don't see it in the Verilog 2001 spec, so that may be something specific to Modelsim. Or it could be the source of the "function not supported."
I have a simple verilog program that increments a 32 bit counter, converts the number to an ASCII string using $sformat and then pushes the string to the host machine 1 byte at a time using an FTDI FT245RL.
Unfortunately Xilinx XST keeps optimizing away the string register vector. I've tried mucking around with various initialization and access routines with no success. I can't seem to turn off optimization, and all of the examples I find online differ very little from my initialization routines. What am I doing wrong?
module counter(CK12, TXE_, WR, RD_, LED, USBD);
input CK12;
input TXE_;
output WR;
output RD_;
output [7:0] LED;
inout [7:0] USBD;
reg [31:0] count = 0;
reg [7:0] k;
reg wrf = 0;
reg rd = 1;
reg [7:0] lbyte = 8'b00000000;
reg td = 1;
parameter MEM_SIZE = 88;
parameter STR_SIZE = 11;
reg [MEM_SIZE - 1:0] str;
reg [7:0] strpos = 8'b00000000;
initial
begin
for (k = 0; k < MEM_SIZE; k = k + 1)
begin
str[k] = 0;
end
end
always #(posedge CK12)
begin
if (TXE_ == 0 && wrf == 1)
begin
count = count + 1;
wrf = 0;
end
else if (wrf == 0) // If we've already lowered the strobe, latch the data
begin
if(td)
begin
$sformat(str, "%0000000000d\n", count);
strpos = 0;
td = 0;
end
str = str << 8;
wrf = 1;
strpos = strpos + 1;
if(strpos == STR_SIZE)
td = 1;
end
end
assign RD_ = rd;
assign WR = wrf;
assign USBD = str[87:80];
assign LED = count[31:24];
endmodule
Loading device for application
Rf_Device from file '3s100e.nph' in
environment /opt/Xilinx/10.1/ISE.
WARNING:Xst:1293 - FF/Latch str_0
has a constant value of 0 in block
. This FF/Latch will be
trimmed during the optimization
process.
WARNING:Xst:1896 - Due to other
FF/Latch trimming, FF/Latch str_1
has a constant value of 0 in block
. This FF/Latch will be
trimmed during the optimization
process.
WARNING:Xst:1896 - Due to other
FF/Latch trimming, FF/Latch str_2
has a constant value of 0 in block
. This FF/Latch will be
trimmed during the optimization
process.
The $sformat task is unlikely to be synthesisable - consider what hardware the compiler would need to produce to implement this function! This means your 'str' register never gets updated, so the compiler thinks it can optimize it away. Consider a BCD counter, and maybe a lookup table to convert the BCD codes to ASCII codes.
AFAIK 'initial' blocks are not synthesisable. To initialize flops, use a reset signal. Memories need a 'for' loop like you have, but which triggers only after reset.