In the below quesiton
A DRAM has 11 multiplexed address pin and one data input/output pin.
14-non multiplexed address pin and 4 data input/output pin Determine
the organization of the DRAM
what are multiplexed address pins and non-multiplexed address pins?
Multiplexed address pins in the context of DRAM means that you can address a row or a column on the same set of pins. First you'd write the row address to the pins and assert RAS (row address select) to tell DRAM to latch the data for the row. Then you'd place the column address on the pins and assert CAS (column address select) to tell the DRAM to latch the data for the column. At this point, the DRAM will read or write data for that row:column on the in/out pin, depending on what you've told it to do with your R/W select pin.
Non-multiplexed pins mean that the row and column are encoded in the entire address. You write the address, and the DRAM reads or writes a data word at that address.
From this info you can probably figure out the total address space. And your data width is given, right?
Here's a paper that explains multiplexed DRAM in more detail. And if you're still having trouble, you may be able to find more info in What Every Programmer Should Know About Memory, Chapter 2.
Related
From the manual shown bellow the address is 0x40 the measure temperature command 0xE3.
From the readback diagram
first master sends slave address and measure command,then We send slave Adress.
But we cant see in the diagram where is the measured data,how it transfered back?
The manual doesnt say what is MS Byte,MS Byte.
Thanks.
https://www.silabs.com/documents/public/data-sheets/Si7021-A20.pdf
The measured data is contained in the MS Byte and the LS Byte. The measured data is a two-byte value. MS Byte is the most significant byte. LS Byte is the least significant byte.
In the diagram, the unshaded cells represent data transmitted from the master to the slave.
And shaded cells represent data received by the master from the slave.
I'm working with mips.
I am confused between machine code and mips code.
if I use mips I can see the addresses of the branch is in number of words we need to jump from the instruction after the branch .
what I don't understand is how it work "behind the sceen" ? and how the "shift left" by 2 is involved in this case?
I need the word to be aligned by 4 byte(word) so actually the address that I see in mips languge is the number of word *4 =number of bytes we need to skeep?
another question:
if the shift left was by 3? what can happend? it will give me the wrong address?
In the MIPS architecture, branching is done by comparing a value as soon as the instruction is given, relying on no previous operation or flag. This takes up space in the instruction format, leaving only 16 bits to be used as the branch address. This is much too small of an address to be particularly useful, so instead of branching to that address, it branches relative to it's own address. The calculation of this branch offset is handled all by the assembler, so it looks like a branch operation would branch directly to a label/address.
Source: http://www.mrc.uidaho.edu/mrc/people/jff/digital/MIPSir.html
In the usb specification (Table 5-4) is stated that given an isochronous endpoint with a maxPacketSize of 128 Bytes as much as 10 transactions can be done per frame. This gives 128 * 10 * 1000 = 1.28 MB/s of theorical bandwidth.
At the same time it states
The host must not issue more than 1 transaction in a single frame for a specific isochronous endpoint.
Isn't it contradictory with the aforementioned table ?
I've done some tests and found that only 1 transaction is done per frame on my device. Also, I found on several web sites that just 1 transaction can be done per frame(ms). Of course I suppose the spec is the correct reference, so my question is, what could be the cause of receiving only 1 packet per frame ? Am I misunderstanding the spec and what i think are transactions are actually another thing ?
The host must not issue more than 1 transaction in a single frame for a specific isochronous endpoint.
Assuming USB Full Speed you could still have 10 isochronous 128 byte transactions per frame by using 10 different endpoints.
The Table 5-4 seems to miss calculations for chapter 5.6.4 "Isochronous Transfer Bus Access Constraints". The 90% rule reduces the max number of 128 byte isochr. transactions to nine.
In the MS-assisted case, it is the GPS receiver which sends the measurements for the SLP to calculate and revert. I understand the measurements include the Ephemeris, Iono, DGPS etc + Doppler shift that are sent. Please let me know if my understanding is right.
Does the SET send the code (the entire data transmitted by satellites as is) that it receives as is or splits it into the above components and send?
All the assistance information in SUPL is encapsulated using RRLP protocol (Radio resource location services (LCS) protocol for GSM), RRC (Radio Resource Control for UMTS) or TIA 801 (for CDMA 2000) or LPP (LTE Positioning Protocol for LTE). I'm just looking at RRLP standard ETSI TS 101 527. The following part sounds interesting:
A.3.2.5 GPS Measurement Information Element
The purpose of the GPS Measurement Information element is to provide
GPS measurement information from the MS to the SMLC. This information
includes the measurements of code phase and Doppler, which enables the
network-based GPS method where position is computed in the SMLC. The
proposed contents are shown in table A.5 below, and the individual
fields are described subsequently.
In subsequent section it is defined as:
reference frame - optional, 16 bits - the frame number of the last measured burst from the reference BTS modulo 42432
GPS TOW (time of week) - mandatory, 24 bits, unit of 1ms
number of satellites - mandatory, 4 bits
Then for each satellite the following set of data is transmitted:
satellite ID - 6 bits
C/No - 6 bits
Doppler shift - 16 bits, 0.2Hz unit
Whole Chips - 10 bits
Fractional Chips - 10 bits
Multipath Indicator - 2 bits
Pseudorange Multipath Error - 3+3 bits (mantissa/exponent)
I'm not familiar that much with GPS operation to understand all the parameters, but as far as I understand:
C/No is simply a signal(carrier) to noise ratio
Doppler shift - gives the frequency shift for a given satellite, obviously
Whole/Fractional Chips together give the phase (and thus satellite distance)
My understanding is that things like almanac, ephemeris, Iono, DGPS are all known on the network side. As far as I know those things are transferred from network to MS in MS-based mode.
Hope that helps.
Measurements collected from MS-assisted location requests include:
Satellite ID
code phase - whole chips
code phase - fractional chips
Doppler
Signal strength
Multipath indicator
pseudorange RMS indicator
In addition, the GPS time of measurements is also provided as one value (in milliseconds) for the time which all measurements are valid.
In practice, the required fields that need to be accurate and correct are:
Satellite ID
code phase - whole chips
code phase - fractional chips
Doppler
The code phase values for each satellite are almost always used for the most accurate location calculation. Doppler values can be used to estimate a rough location but aren't usually accurate enough to really contribute to the final solution.
The other values for signal strength, multipath indication, and RMS indicator usually vary in meaning so much between vendors that they don't really provide much benefit for the position calculation. They would normally be used for things like weighting other values so that good satellites count more in the final position.
The network already knows (or should know) the ephemeris and ionospheric model. They are not measurements collected by the handset.
I have another exercice that I couldn't resolve,
A central memory composed by two memory module(RAM).the total address range attributed to the central memory is:
FROM 0000 0000H TO 3FFF FFFFH
1/Give the total capacity of the central memory (Megabyte and Gegabyte)
2/Give the capacity of each memory module(RAM)
3/Give the first and last address of each memory module(RAM)
Sorry for the bad translation the exercice is an french.
Well, 1 is easy. The range from 0000 0000H to 3FFF FFFFH contains 4000 0000H addresses. (Just like 0 to 3 is four addresses, 0, 1, 2, and 3.) 4000 0000H is 1,073,741,824 decimal, or 1GB. 1,024 MB.
2 is no problem. If two memory modules give 1GB, then each module must be 512MB.
3 is impossible. We don't know if the memory modules are consecutive or interleaved. But if we assume they're consecutive, which I imagine is what the exercise wants us to do, then the first one must be 0000 0000H to 1FFF FFFFH and the second one must be 2000 0000H to 3FFF FFFFH.
Note that mapping memory modules consecutively is generally considered dumb. It means that in the typical case where the memory module bandwidth is the limiting factor, if an application is only using the first half of memory, it's only using one of the two modules, wasting half the available memory bandwidth. (Though, in the less common case where the memory is as fast or faster than the CPU or its memory bus, it doesn't matter.)