I'm getting a syntax error at 11 line
Full adder using xor and mux2x1
module xormux(x1, x2, x3, y1, y2);
input x1, x2, x3;
output y1, y2;
wire w1, w2;
xor gate1(w1, x1, x2);
xor gate2(y1, w1, x3);
mux2x1 gate3(y2, w1, x3, x2);
endmodule
module xor(output o, input i1, i2);
assign o = i1 ^ i2;
endmodule
module mux2x1(output o, input i1, i2, s);
assign o = s ? i2 : i1;
endmodule
Full adder using xor and mux2x1
xor is a reserved keyword in Verilog, per Table 22-1 in the standard (see IEEE Std 1800-2017, "22.14.2 IEEE 1364-1995 keywords").
Use a different identifier for your module.
Related
In Code A, the parameters x1 and x2 use the same vaule, it works well.
I think I can improve Code A, so I write Code B, but it failed.
How can I assign x2 with the value of x1 ?
Code A
val stepWidth = step * index
it.drawChildnAxis(
x1 = stepWidth.toX, y1 = 0f.toY,
x2 = stepWidth.toX, y2 = yAxisLength.toY
)
fun Canvas.drawChildnAxis(x1:Float, y1:Float,x2:Float,y2:Float){
drawLine(
Offset(x = x1, y = y1),
Offset(x = x2, y = y2),
paintTableAxisChild
)
}
Code B
it.drawChildnAxis(
x1 = step * index.toX, y1 = 0f.toY,
x2 = x1, y2 = yAxisLength.toY
)
//The same
The x1 = ..., x2 = ... etc in your code are not actually assignment statements! They are named arguments.
There is no variable x1, x2 etc that becomes suddenly in scope at the function call, allowing you to assign values to it. This is just a bit of a syntax that lets you say the names of your parameters to make your code more readable, and sometimes resolve overload resolution ambiguities.
The syntax just so happened to be designed to look similar to assignments, making the left hand side look like a new variable just got declared. Would you still have this confusion if the syntax used : instead of =?
it.drawChildnAxis(
x1: stepWidth.toX, y1: 0f.toY,
x2: stepWidth.toX, y2: yAxisLength.toY
)
So x2 = x1 doesn't make sense - there is no such variable as x1 at that position. x1 is only the name of a parameter, which is only in scope when you are inside drawChildnAxis.
If you want to avoid repetition, just create a new variable yourself!
val x = stepWidth.toX
it.drawChildnAxis(
x1 = x, y1 = 0f.toY,
x2 = x, y2 = yAxisLength.toY
)
If you don't want x to be accessible afterwards, use a scope function:
stepWidth.toX.let { x ->
it.drawChildnAxis(
x1 = x, y1 = 0f.toY,
x2 = x, y2 = yAxisLength.toY
)
}
All of this is of course assuming that toX doesn't have side effects - calling its getter twice on the same thing gives the same value.
I have a certain dataset in R language, let's say
A<- data.frame(1:5)
B<- data.frame(1:5)
C<- data.frame(1:5)
D<- data.frame(1:5)
and 4 equation with 4 knowns X1, X2, X3 and X4
equ1<-A*(x[3]+x[4]+x[1])-x[2]*(x[3]+x[4]+x[1]-A)
equ2<-B*(x[2]+x[4]+x[1])-x[3]*(x[2]+x[4]+x[1]-B)
equ3<-C*(x[2]+x[3]+x[1])-x[4]*(x[2]+x[3]+x[1]-C)
equ4<-D*(x[2]+x[3]+x[4])-x[1]*(x[2]+x[3]+x[4]-D)
where each row in columns A, B, C, and D should go through this nonlinear equation to simultaneously solve, and output which will be X1, X2, X3, and X4 should be in a different column.
For A=21, B=223, C=232, and D=432
This code is working but not for the data frame.
library("nleqslv")
A<- data.frame(1:5)
B<- data.frame(1:5)
C<- data.frame(1:5)
D<- data.frame(1:5)
fn <- function(x[i])
x<-as.data.frame(x)
{
equ1<-A*(x[3]+x[4]+x[1])-x[2]*(x[3]+x[4]+x[1]-A)
equ2<-B*(x[2]+x[4]+x[1])-x[3]*(x[2]+x[4]+x[1]-B)
equ3<-C*(x[2]+x[3]+x[1])-x[4]*(x[2]+x[3]+x[1]-C)
equ4<-D*(x[2]+x[3]+x[4])-x[1]*(x[2]+x[3]+x[4]-D)
return(c(equ1,equ2,equ3,equ4))
}
}
sol=nleqslv(c(A, B,C,D),FUN=fn)
v<-sol$x[1]
x<-sol$x[2]
y<-sol$x[3]
z<-sol$x[4]
v
x
y
z
Waitng for you guys to provide me a solution.
PROGRAM 6: Same
Write an HLA Assembly language program that implements a function which correctly identifies when all four parameters are the same and returns a boolean value in AL (1 when all four values are equal; 0 otherwise). This function should have the following signature:
procedure theSame( w:int16; x:int16; y:int16; z:int16 ); #nodisplay; #noframe;
Shown below is a sample program dialogue.
Feed Me W: 215
Feed Me X: 215
Feed Me Y: 480
Feed Me Z: 91
Not the same. AL = 0
Feed Me W: 0
Feed Me X: 0
Feed Me Y: 0
Feed Me Z: 0
Same. AL = 1
Feed Me W: 0
Feed Me X: 221
Feed Me Y: 100
Feed Me Z: 40
Not the same. AL = 0
**My output are almost correct but when I entered
w : 2
x : 2
y : 2
z : 1
"the same" instead of "NOT the same"
Please help with any thoughts that I might be missing.**
I am not sure if register push and pop are the issue.
program Same;
#include ("stdlib.hhf");
static
iDataValue1 : int16 := 0;
iDataValue2 : int16 := 0;
iDataValue3 : int16 := 0;
iDataValue4 : int16 := 0;
procedure theSame( w : int16; x : int16; y : int16; z : int16); #nodisplay; #noframe;
static
returnAddress : dword;
temp: int16;
begin theSame;
pop (returnAddress);
pop (temp);
pop (z);
pop (y);
pop (x);
pop (w);
push (returnAddress);
push (BX);
//Perform Subtask
mov (z, BX);
cmp (y, BX); // Compare z & y
jne ReturnZero;
mov (y, BX);
cmp (x, BX); // Compare y & x
je ReturnOne;
jmp ReturnZero;
mov (x, BX);
cmp (w, BX); // Compare x & w
je ReturnOne;
jmp ReturnZero;
ReturnOne:
mov (1, AL);
jmp ExitSequence;
ReturnZero:
mov (0, AL);
jmp ExitSequence;
ExitSequence:
pop (BX);
ret();
end theSame;
begin Same;
stdout.put ("Feed Me W: ");
stdin.get (iDataValue1);
stdout.put ("Feed Me X: ");
stdin.get (iDataValue2);
stdout.put ("Feed Me Y: ");
stdin.get (iDataValue3);
stdout.put ("Feed Me Z: ");
stdin.get (iDataValue4);
push (iDataValue1);
push (iDataValue2);
push (iDataValue3);
push (iDataValue4);
call theSame;
cmp (AL, 1);
je NumbersAreSame;
jmp NumbersAreDifferent;
NumbersAreSame:
stdout.put ("Same. AL = 1");
jmp EndProgram;
NumbersAreDifferent:
stdout.put ("Not the same. AL = 0");
stdout.newln();
jmp EndProgram;
EndProgram:
end Same;
ENVIRONMENT
HLA (High Level Assembler - HLABE back end, LD linker)
Version 2.16 build 4463 (prototype)
Ubuntu 20.10
SOLUTION
Five values are pushed to the stack when calling theSame(), those are the return address, w, x, y, and z. However in the prologue for theSame() six values are currently popped off of the stack.
begin theSame;
pop (returnAddress);
pop (temp);
pop (z);
pop (y);
pop (x);
pop (w);
The additional pop (temp); seen above causes the temp variable to store the value passed in for z, z to store the value passed in for y, y to store the value passed in for x, x to store the value passed in for w, and w to store the next random value on the stack. Removing the pop (temp); instruction will result in your example case passing.
Feed Me W: 2
Feed Me X: 2
Feed Me Y: 2
Feed Me Z: 1
Not the same. AL = 0
However the following case will still fail due to errors in the comparison logic.
Feed Me W: 1
Feed Me X: 2
Feed Me Y: 2
Feed Me Z: 2
Same. AL = 1
In the following code if z, y, and x are equal then the code will jump to ReturnOne with out checking the value of w. This is corrected by removing the first je ReturnOne; and changing the first jmp ReturnZero; to jne ReturnZero;.
mov (z, BX);
cmp (y, BX); // Compare z & y
jne ReturnZero;
mov (y, BX);
cmp (x, BX); // Compare y & x
je ReturnOne;
jmp ReturnZero;
mov (x, BX);
cmp (w, BX); // Compare x & w
je ReturnOne;
jmp ReturnZero;
EXAMPLE
program Same;
#include("stdlib.hhf");
procedure theSame(w: int16; x: int16; y: int16; z: int16); #nodisplay; #noframe;
begin theSame;
pop(EDX); // Return Address
pop(z);
pop(y);
pop(x);
pop(w);
push(EDX); // Return Address
mov(z, BX);
cmp(y, BX); // Compare z & y
jne ReturnZero;
mov(y, BX);
cmp(x, BX); // Compare y & x
jne ReturnZero;
mov(x, BX);
cmp(w, BX); // Compare x & w
jne ReturnZero;
mov(1, AL);
jmp ExitSequence;
ReturnZero:
mov(0, AL);
ExitSequence:
ret();
end theSame;
begin Same;
stdout.put("Feed Me W: ");
stdin.geti16();
push(AX);
stdout.put("Feed Me X: ");
stdin.geti16();
push(AX);
stdout.put("Feed Me Y: ");
stdin.geti16();
push(AX);
stdout.put("Feed Me Z: ");
stdin.geti16();
push(AX);
call theSame;
cmp(AL, 1);
jne NumbersAreDifferent;
stdout.put("Same. AL = 1");
jmp EndProgram;
NumbersAreDifferent:
stdout.put("Not the same. AL = 0");
EndProgram:
end Same;
I am just beginning to learn verilog. I wrote two programs for that purpose. Here is my first program:
module test1(i,o);
input i;
output o;
wire[0:63] i;
wire[0:63] o;
assign o = i * 2.0;
endmodule
module test1_tb();
reg[0:63] inp;
wire[0:63] outp;
initial
begin
assign inp = 2.0;
$monitor("input=%f, output=%f",inp,outp);
end
test1 t1(inp,outp);
endmodule
This gives me the following result when I run it in ModelSim:
# input=2.000000, output=4.000000
Then I edited the above program as follows:
module test1(i1,i2,h1,w1,w2,b1);
input i1;
input i2;
input w1;
input w2;
input b1;
output h1;
wire[0:63] i1;
wire[0:63] i2;
wire[0:63] h1;
wire[0:63] w1;
wire[0:63] w2;
wire[0:63] b1;
assign h1 = 1/(1+ 2.718281828459**((-1.0)*(i1 * w1 + i2 * w2 + b1)));
endmodule
module test1_tb();
reg[0:63] i1;
reg[0:63] i2;
reg[0:63] w1;
reg[0:63] w2;
reg[0:63] b1;
wire[0:63] h1;
initial
begin
assign i1 = 0.05;
assign i2 = 0.10;
assign w1 = 0.15;
assign w2 = 0.20;
assign b1 = 0.35;
$monitor("i1=%f, i2=%f, w1=%f, w2=%f, b1=%f, h1=%f",i1,i2,w1,w2,b1,h1);
end
test1 n1(i1,i2,h1,w1,w2,b1);
endmodule
For this program I get the output:
# i1=0.000000, i2=0.000000, w1=0.000000, w2=0.000000, b1=0.000000, h1=1.000000
It seems the module does not get the initial values in the second program. But all I did was adding few more input lines to the first program and changing the calculation.
Right now I don't know what's the error with this. Please help.
The type reg is not designed to implicitly handle floating point math. As such, real constants assigned to the reg variables are rounded to the nearest integer (see IEEE1800-2012 Section 5.7.2, SystemVerilog LRM; sorry I dont have IEEE1364, Verilog LRM, to find the reference in there).
If you simply want to do some floating point math, you can use the real type which is the same as a double. Otherwise, if you want to do floating point math in hardware, youll need to deal with the complexities of it yourself (or borrow from an IP core). Also note that Verilog is not a scripting language, but a Hardware Descriptive Language, so unless you are trying to design hardware, you are much better off using Python, Ruby or Perl for general purpose stuff.
Hello I am trying to implement the gate MiniALU but the howard simulator give me this error: "has no source pin". I would be happy if you can help me solve this.
my code-
CHIP MiniALU {
IN
x[16], y[16], // 16-bit inputs
zx, // zero the x input?
zy, // zero the y input?
f; // compute out = x + y (if f == 1) or out = x & y (if == 0)
OUT
out[16]; // 16-bit output
PARTS:
// Zero the x input and y input
Mux16(a[0..15]=x, b[0..15]=false, sel=zx, out[0..15]=x1);
Mux16(a[0..15]=y, b[0..15]=false, sel=zy, out[0..15]=y1);
// Perform f
And16(a[0..15]=x2, b[0..15]=y2, out[0..15]=xandy);
Add16(a[0..15]=x2, b[0..15]=y2, out[0..15]=xaddy);
Mux16(a[0..15]=xandy, b[0..15]=xaddy, sel=f, out[0..15]=out);
}
You are connecting x2 and y2 to the inputs of And16 and Add16 but x2 and y2 are not defined anywhere.
You need to replace x2 and y2 with x1 and y1 in the connections to And16 and Add16.
Correct code:
Mux16(a=x, b=false, sel=zx, out=x1);
Mux16(a=y, b=false, sel=zy, out=y1);
And16(a=x1, b=y1, out=xandy);
Add16(a=x1, b=y1, out=xaddy);
Mux16(a=xandy, b=xaddy, sel=f, out=out);
Your problem was that you wrote y2 and x2 instead of y1 and x2.
Also, there is not need in [0..15]
You wrote:
And16(a[0..15]=x2, b[0..15]=y2, out[0..15]=xandy);
Add16(a[0..15]=x2, b[0..15]=y2, out[0..15]=xaddy);
instead of:
And16(a[0..15]=x1, b[0..15]=y1, out[0..15]=xandy);
Add16(a[0..15]=x1, b[0..15]=y1, out[0..15]=xaddy);