Pump Valve On/Off Regulation for Certain Time - fluid

In Switzerland, the heating period usually lasts from mid-September to mid-May.
Is there any possibility to set either valve or pump to closed (0 if y=true) position from e.g., 15.05 till 15.09 in the simulation?

The easiest will be to use the Modelica.Blocks.Sources.RealExpressionas the RealInput to Modelica.Fluid.Valves.ValveIncompressible component. You can assign Modelica.Blocks.Sources.RealExpression.y= if (time > 15.05) and (time < 15.09) then 1 else 0.01. In fluidpackages it is advisable not to set the valve close value explicitly as '0' but to positive value close to 0 say 0.01.

Related

What is the Difference between Aging and Healing in AUTOSAR DEM?

Event Aging
The process of aging resets status bit 3 – ConfirmedDTC when a sufficient amount of time
has elapsed so that the cause for the error entry is assumedly not relevant anymore. This
is often used as a trigger to also clear stored snapshots or extended data from the event
memory.
But I don't get the healing process. I couldn't find anything about it.
Aged counter
Aging Counter The Dem module provides the ability to remove a specific event from the event memory, if its fault conditions are not fulfilled for a certain period of time (operation cycles). This process is called as "aging" or "unlearning". The usage of this feature requires the maintaining of an additional NVRAM block
Healing counter
Available both in positive direction, counting up from 0 (healing not started), latching at 255;
and in reverse counting down from the healing threshold (healing not started) to 0. The
counter is incremented resp. decremented as soon as the healing conditions are fulfilled (at
the end of a ‘passed’ tested operation cycle without failed result), irrespective of the status
of the ‘ConfirmedDTC ‘ or ‘WarningIndicatorRequested’ status bit.
The up-counting data element corresponds to ‘Cycles Tested Since Last Failed’.
Both data elements are also calculated for events without indicator.
I found the following Diagram in AUTOSAR documentation, now It's clear
According to AUTOSAR DEM SWS Document :
Healing of diagnostic events
The Dem module provides the ability to activate and deactivate indicators per event
stored in the event memory. The process of deactivation is defined as healing of a
diagnostic event.
Aging of diagnostic events
The Dem module provides the ability to remove a specific event from the event memory, if its fault conditions are not fulfilled for a certain period of time (operation cycles).This process is called as "aging" or "unlearning".
Few points to notice ( According to my point of view ) :
1 - Each one of them has a separate counter and a separate threshold, When the counting value meets the provided threshold, corresponding action is being taken.
2 - Normally, healing comes before aging.
3 - Aging resets the confirmedDTC bit in the status byte of the DTC. Healing just means we have an operation cycle in which the event status byte never had the testFailedThisOperationCycle bit set before.

Create a variable to count from 1 to n in AnyLogic

I am looking to add a variable to count from 1 to 217 every hour in AnyLogic, in order to use as a choice condition to set a parameters row reference.
I am assuming I either need to use an event or a state chart however I am really struggling with the exact and cannot find anything online.
If you have any tips please let me know, any help would be appreciated
Thank you,
Tash
A state machine isn't necessary in this case as this can be achieve using a calculation or a timed event. AnyLogic has time() function which returns time since model start as a double in model time units of measurements.
For example: if model time units is seconds and it has been running for 2hr 2min 10sec then time(SECOND) will return 7330.0 (it is always a double value). 1/217th of an hour corresponds to about 3600/217 = 16.58 seconds. Also, java has a handy function Math.floor() which rounds down a double value, so Math.floor(8.37) = 8.0.
Assembling it all together:
// how many full hours have elapsed from the start of the model
double fullHrsFromStart = Math.floor(time(HOUR));
// how many seconds have elapsed in the current model hour
double secondsInCurrentHour = time(SECOND) - fullHrsFromStart * 3600.0;
// how many full 16.58 (1/217th of an hour) intervals have elapsed
int fullIntervals = (int)(secondsInCurrentHour / 16.58);
This can be packaged into a function and called any time and it is pretty fast.
Alternatively: an Event can be created which increments some count by 1 every 16.58 seconds and ten resets it back to 0 when the count reaches 217.

measuring time between two rising edges in beaglebone

I am reading sensor output as square wave(0-5 volt) via oscilloscope. Now I want to measure frequency of one period with Beaglebone. So I should measure the time between two rising edges. However, I don't have any experience with working Beaglebone. Can you give some advices or sample codes about measuring time between rising edges?
How deterministic do you need this to be? If you can tolerate some inaccuracy, you can probably do it on the main Linux OS; if you want to be fancy pants, this seems like a potential use case for the BBB's PRU's (which I unfortunately haven't used so take this with substantial amounts of salt). I would expect you'd be able to write PRU code that just sits with an infinite outerloop and then inside that loop, start looping until it sees the pin shows 0, then starts looping until the pin shows 1 (this is the first rising edge), then starts counting until either the pin shows 0 again (this would then be the falling edge) or another loop to the next rising edge... either way, you could take the counter value and you should be able to directly convert that into time (the PRU is states as having fixed frequency for each instruction, and is a 200Mhz (50ns/instruction). Assuming your loop is something like
#starting with pin low
inner loop 1:
registerX = loadPin
increment counter
jump if zero registerX to inner loop 1
# pin is now high
inner loop 2:
registerX = loadPin
increment counter
jump if one registerX to inner loop 2
# pin is now low again
That should take 3 instructions per counter increment, so you can get the time as 3 * counter * 50 ns.
As suggested by Foon in his answer, the PRUs are a good fit for this task (although depending on your requirements it may be fine to use the ARM processor and standard GPIO). Please note that (as far as I know) both the regular GPIOs and the PRU inputs are based on 3.3V logic, and connecting a 5V signal might fry your board! You will need an additional component or circuit to convert from 5V to 3.3V.
I've written a basic example that measures timing between rising edges on the header pin P8.15 for my own purpose of measuring an engine's rpm. If you decide to use it, you should check the timing results against a known reference. It's about right but I haven't checked it carefully at all. It is implemented using PRU assembly and uses the pypruss python module to simplify interfacing.

Static timed loop in objective-c cocos2d?

Looking for some ideas on how to implement this, don't necessarily need the exact code.
Let's say I have a game where the player's hit points are displayed in a label, say 100HP. When he takes damage, say 30 damage, I want that label to count down from 99, 98 , 97 ... 70. It should take 2 seconds to perform the countdown whether you take 30 damage or 3000 damage.
I'm wondering what's the most efficient way to get this loop to count down "smoothly" over 2 seconds no matter what the damage taken is.
I'd probably extend a CCLabelSomething to do that, embedding the desired behaviour. Suggest a fixed width font, otherwise nothing smooth will happen (visually). Figure out what is 'smooth for you', ie how many updates in the 2 second period. in the assumed 'setScore' public method, start a scheduled update cycle with appropriate delay. In the schedule callback, change the text of the label.
say 20 updates, ie 10 per seconds. Schedule with .1f delay between intervals. Upon setScore, compute the 'delta' per update (currentScore - newScore)/20. Decrement currentScore down to newScore by this delta. In the schedule callBack, stop your scheduled update if the displayed score is equal to the newScore.

VHDL: Properly clocking another component with respect to setup

I am working on a FPGA project in VHDL.
I need to copy a 16 bit shift register into a FIFO each time it fills up (eg after 16 new data bits have been fed into the shift register, I want to take the newly formed 16 bit word and send it to a fifo)
My question is, do I need to set up the data at the input of the fifo one clock before asserting the clock line on the fifo? This is actually a generic VHDL question, and not specific to fifos.
Basically, is it possible to set the data and toggle the clock in the same operation, or do I need some basic state machine to set up the data on one clock edge and toggle the fifo clock on the next?
for instance:
fifo_d_in( 7 downto 0 ) <= shift_register;
fifo_clk <= '1';
or
if( state = one ) then
fifo_d_in( 7 downto 0 ) <= shift_register;
state <= two;
elsif( state = two ) then
fifo_clk <= '1';
end if;
My gut tells me that I have to setup the data first, to satisfy the setup & hold requirements of the input registers.
Thanks!
The data must be present for the setup time before the clock edge, so asserting the clock at the same time as any possible data changes may result in unstable behaviour.
One way to configure your shift register is to have an output which asserts after the last bit of data has been clocked in. For an 8 bit shift register, after the 8th clock the signal would be asserted. Any easy way to accomplish this is with a 3 bit counter, when all bits are 1 the output is 1. This signal is then connected to the CLKEN of your fifo so that on the 9th clock edge, the data at the output of your shift register is clocked into the the fifo. It would also be possible to clock in the next serial bit of data to your shift register on the 9th clock.
shift reg FIFO
------------- ---------
-|DIN DOUT |--------| DIN |
| FULL |--------| CLKEN |
- |> | --|> |
| ------------- | ---------
| |
CLK -----------------------
In the above diagram, FULL would be asserted the instant after the last bit of data was clocked in to fill the shift register, and deasserted on the next cycle. FULL can be combinatorial logic.