Why is DMux4way operate like this? - hdl

Question

When the sel is 01 the b should be chosen, but why the operation is a = nsel1 b = sel[0]? After that the sel will become 00 from 01
CHIP DMux4Way {
IN in, sel[2];
OUT a, b, c, d;
PARTS:
// Put your code here:
Not(in = sel[0], out = nsel0);
Not(in = sel[1], out = nsel1);
And(a = nsel1, b = nsel0, out = s00);
And(a = in, b = s00, out = a);
And(a = nsel1, b = sel[0], out = s01);
And(a = in, b = s01, out = b);
And(a = sel[1], b = nsel0, out = s10);
And(a = in, b = s10, out = c);
And(a = sel[1], b = sel[0], out = s11);
And(a = in, b = s11, out = d);
}

Answer 1

I just figured it out because the hack uses little endian.

Answer 2

In each pair of ANDs, the first one determines whether the output is activated, and the second one gates the input to that output.
So:
And(a = nsel1, b = nsel0, out = s00);
s00 is True only if both its inputs (nsel0 and nsel1) are True. Since they are the inverse of sel[0] and sel[1], s00 will only be true if both sel[0] and sel[1] are False.
And(a = in, b = s00, out = a);
The second And will only be true if both in and s00 are True. So it will only be True if in is True, and sel[0] and sel[1] are False.
Similar logic applies for the other cases. But the key point is that for the 01 and 10 cases, it is not enough to check that the right value is True, you also have to check that the other value is 0.
Edit: In addition, as the OP points out in a subsequent comment, the machine is little-endian, and you must keep this in mind when operating on a multi-bit bus (like sel).