Checker not found. promblem in verilog modelsim - module

Question

module Vr_ALU (A, B, ALUCtrl, ALUOut, Zero);
input [31:0] A;
input [31:0] B;
input [2:0] ALUCtrl;
output [31:0] ALUOut;
output Zero;
wire [31:0] sig_a;
wire [31:0] sig_b;
wire [31:0] sig_sum;
wire sig_cin;
wire sig_cout;
always #(*) begin
if(ALUCtrl==2'b010)
Vr_ripple_adder_M_bits U1(.A(sig_a), .B(sig_b), .CIN(sig_cin), .S(sig_sum), .COUT(sig_cout));
else if(ALUCtrl==2'b110)
Vr_ripple_adder_M_bits U2(.A(sig_a), .B(~sig_b), .CIN(~sig_cin), .S(sig_sum), .COUT(~sig_cout));
else ALUOut = 2'bx;
end
assign Zero = (ALUCtrl==2'b110 && ALUOut==0)? 1:0;
endmodule
at this code, I try to make module work as adder when ALUCtrl is 010, and as subtractor when ALUCtrl is 110. But I'm having 'checker not found. Instantiation must be of a visible checker' problem.
Need help.

Answer 1

You cannot instantiate modules in always blocks. You cannot instantiate module conditionally. Modules represent hardware and as such they are always present.
Instead you can use muxes to switch inputs in your module. For example,
reg[31:0] sig_b_temp;
reg sig_cin_temp;
reg sig_cout_temp;
reg sig_cout; // uou need 'reg' for this example.
// muxes
always #(*) begin
if(ALUCtrl==2'b010) begom
//inuts
sig_cin_temp = sig_sin;
sig_b_temp = sig_b;
//outputs
sig_cout = sig_cout_temp;
end
else begin
//inputs
sig_cin_temp = ~sig_sin;
sig_b_temp = ~sig_b;
//output
sig_cout = ~sig_cout_temp;
end
end
//single module instance
Vr_ripple_adder_M_bits U1(.A(sig_a),
.B(sig_b_temp),
.CIN(sig_cin_temp),
.S(sig_sum),
.COUT(sig_cout_temp));
Note, the code above will not compile with