module HazardDetectionUnit(stall, Rs1, Rt1, Rt2, MemRead2, clk);
input clk, MemRead2;
input [4:0] Rs1, Rt1, Rt2;
output reg [2:0] stall;
always #(negedge clk)
begin
if(MemRead2 & ((Rt2 = Rs1) | (Rt2 = Rt1))) //Error has been detected in this line
stall <= 3'b000;
else
stall <= 3'b111;
end
endmodule
ERROR: /nfs/home/s/s_ankith/HazardDetectionUnit_MIPS.v(7): near ")":
Syntax error. Assignment sub-exprs. are only allowed in SystemVerilog
or PSL.
You need == for testing equality:
if(MemRead2 & ((Rt2 == Rs1) | (Rt2 == Rt1)))
Related
I have a problem in PISO verilog register.
Below is my code
`timescale 1ns / 1ps
module PISO(
input clk,
input load,
input [3:0] d,
output reg Qout);
reg [3 : 0]Q;
always # (posedge clk)
begin
if ( load )
Q <= d;
else
begin
Qout <= d[3];
Q<= { Q[2:0] , 1'b0 };
end
end
endmodule
and my testbench
`timescale 1ns / 1ps
module PISO_tb();
PISO uut(clk,load,d,Qout);
reg clk;
reg load;
reg [3:0]d;
wire Qout;
initial begin
clk=0;
forever #5 clk = ~clk;
end
initial begin
load = 1;
d[0] = 1'b0;
d[1] = 1'b1;
d[2] = 1'b0;
d[3] = 1'b1;
#6 load = 0;
end
endmodule
And it isn't working as it should, please help me with testbench maybe? Because I think the verilog code is okay and it should work properly.
You want the Qout signal to be the output of the shift register (Q) instead of the input, so that the output toggles instead of remaining at 1. Change:
Qout <= d[3];
to:
Qout <= Q[3];
I am having a small issue here in when I instantiated my modules. I am using a generate loop to create 100 instances of 2 counters (16 & 32 bit counters). Each counter should have their own independent controls (UPDN & EN), but they share a clock and a reset.
Module Descriptions:
SAT_COUNTER.sv // SIMPLE COUNTER MODULE
TWO_SC.sv // INSTANTIATES TWO SAT_COUNTER MODULES (16 BIT & 32 BIT
COUNTERS)
GEN_SC.sv // INSTANTIATES 100 MODULES OF TWO_SC MODULES
tb_GEN_SC.sv // TESTBENCH
I am sure that my problem is in the GEN_SC module where I instantiate all 100..
I appreciate any help! Thank you in advance!
module SAT_COUNTER(
COUNT, // SCALABLE COUNT OUTPUT
CLK, // CLOCK
al_RST, // ACTIVE LOW RESET
UPDN, // COUNTER WILL COUNT: UP = 1; DN = 0;
EN); // ENABLE
parameter WIDTH = 8;
input CLK, al_RST, UPDN, EN;
output reg [WIDTH-1:0] COUNT;
...
endmodule
//**********************
module TWO_SC(
COUNT1, // N-BIT COUNTER OUTPUT
COUNT2, // M-BIT COUNTER OUTPUT
CLK, // CLOCK
al_RST, // ACTIVE-LOW RESET
UPDN, // DIR. CONTROL
EN); // ENABLE
parameter WIDTH1 = 16;
parameter WIDTH2 = 32;
input CLK, al_RST;
input [1:0] UPDN, EN;
output [WIDTH1-1:0] COUNT1;
output [WIDTH2-1:0] COUNT2;
SAT_COUNTER #(WIDTH1) GSC1(.COUNT(COUNT1), .CLK(CLK), .al_RST(al_RST), .UPDN(UPDN[0]), .EN(EN[0]));
SAT_COUNTER #(WIDTH2) GSC2(.COUNT(COUNT2), .CLK(CLK), .al_RST(al_RST), .UPDN(UPDN[1]), .EN(EN[1]));
endmodule
//**********************
module GEN_SC(
COUNT1, // COUNT1
COUNT2, // COUNT2
CLK, // CLOCK
al_RST, // ACTIVE-LOW RESET
UPDN, // DIR. CONTROL
EN); // ENABLE
parameter MOD_COUNT = 100;
parameter WIDTH1 = 16;
parameter WIDTH2 = 32;
input CLK, al_RST;
input [1:0] UPDN [MOD_COUNT-1:0];
input [1:0] EN [MOD_COUNT-1:0];
output [WIDTH1-1:0] COUNT1;
output [WIDTH2-1:0] COUNT2;
genvar j;
generate
for(j = 0; j < MOD_COUNT; j++) begin: SC
TWO_SC #(.WIDTH1(WIDTH1), .WIDTH2(WIDTH2)) TWOCOUNTERS(.COUNT1(COUNT1), .COUNT2(COUNT2), .CLK(CLK), .al_RST(al_RST), .UPDN(UPDN[j]), .EN(EN[j]));
end
endgenerate
endmodule
//**********************
module tb_GEN_SC();
parameter MOD_COUNT = 100;
parameter WIDTH1 = 16;
parameter WIDTH2 = 32;
reg CLK, al_RST;
reg [1:0] UPDN [MOD_COUNT-1:0];
reg [1:0] EN [MOD_COUNT-1:0];
wire [WIDTH1-1:0] COUNT1;
wire [WIDTH2-1:0] COUNT2;
GEN_SC #(.WIDTH1(WIDTH1), .WIDTH2(WIDTH2)) UUT(COUNT1, COUNT2, CLK, al_RST, UPDN, EN);
initial begin
CLK = 1'b1;
forever
#5 CLK = ~CLK;
end
initial
$monitorb("%d COUNT = %b (%d) | UPDN = %b | EN = %b | COUNT = %b (%d) | UPDN = %b | EN = %b | al_RST = %b | CLK = %b", $time, UUT.SC[87].TWOCOUNTERS.COUNT1, UUT.SC[87].TWOCOUNTERS.COUNT1, UUT.SC[87].TWOCOUNTERS.UPDN[0], UUT.SC[87].TWOCOUNTERS.EN[0], UUT.SC[99].TWOCOUNTERS.COUNT1, UUT.SC[99].TWOCOUNTERS.COUNT1, UUT.SC[99].TWOCOUNTERS.UPDN[0], UUT.SC[99].TWOCOUNTERS.EN[0], al_RST, CLK);
initial begin
$vcdpluson;
UUT.SC[87].TWOCOUNTERS.GSC1.UPDN = 1; UUT.SC[99].TWOCOUNTERS.GSC1.UPDN = 1; EN = 0; al_RST = 1;
#10 UUT.SC[99].TWOCOUNTERS.GSC1.UPDN = 0; al_RST = 0; // RESET COUNTER
#10 EN = 1; al_RST = 1; // ENABLE COUNTER AND COUNT UP (HITS MAX)
#200 UUT.SC[87].TWOCOUNTERS.GSC1.UPDN = 0; UUT.SC[99].TWOCOUNTERS.GSC1.UPDN = 1; EN = 1; // BEGIN TO COUNT DOWN
#10 EN = 0;
#60 EN = 3;
// #230 UPDN = 1; UPDN = 0;
#3017 al_RST = 0;
#100 al_RST = 1;
#20 $finish;
end
/////////// ERRORS I GET /////////////////
Error-[IBLHS-NT] Illegal behavioral left hand side
tb_GEN_SC.sv, 34
Net type cannot be used on the left side of this assignment.
The offending expression is : tb_GEN_SC.UUT.SC[87].TWOCOUNTERS.GSC1.UPDN
Source info: tb_GEN_SC.UUT.SC[87].TWOCOUNTERS.GSC1.UPDN = 1;
Error-[IBLHS-NT] Illegal behavioral left hand side
tb_GEN_SC.sv, 34
Net type cannot be used on the left side of this assignment.
The offending expression is : tb_GEN_SC.UUT.SC[99].TWOCOUNTERS.GSC1.UPDN
Source info: tb_GEN_SC.UUT.SC[99].TWOCOUNTERS.GSC1.UPDN = 1;
Error-[IUDA] Incompatible dimensions
tb_GEN_SC.sv, 34
Incompatible unpacked dimensions in assignment
Arrays with incompatible unpacked dimensions cannot be used in assignments,
initializations and instantiations.
Error-[ICTA] Incompatible complex type
tb_GEN_SC.sv, 34
Incompatible complex type assignment
Type of source expression is incompatible with type of target expression.
Mismatching types cannot be used in assignments, initializations and
instantiations. The type of the target is 'reg[1:0]$[99:0]', while the type
of the source is 'int'.
Source Expression: 0
You have just one UPDB and one EN port in port list. So how you wana apply different UPDN and EN to instances?
An idea is to define an array with size of MOD_COUNT so that each element has its own control input. then in genvar loop you can use the index. like this:
input [1:0] UPDN [MOD_COUNT-1:0];
input [1:0] EN [MOD_COUNT-1:0];
...
generate
for(j = 0; j < MOD_COUNT; j++) begin: SC
TWO_SC #(.WIDTH1(WIDTH1), .WIDTH2(WIDTH2)) TWOCOUNTERS(.COUNT1(COUNT1),
.COUNT2(COUNT2), .CLK(CLK), .al_RST(al_RST), .UPDN(UPDN[j]), .EN(EN[j]));
end
endgenerate
I am just beginning to learn verilog. I wrote two programs for that purpose. Here is my first program:
module test1(i,o);
input i;
output o;
wire[0:63] i;
wire[0:63] o;
assign o = i * 2.0;
endmodule
module test1_tb();
reg[0:63] inp;
wire[0:63] outp;
initial
begin
assign inp = 2.0;
$monitor("input=%f, output=%f",inp,outp);
end
test1 t1(inp,outp);
endmodule
This gives me the following result when I run it in ModelSim:
# input=2.000000, output=4.000000
Then I edited the above program as follows:
module test1(i1,i2,h1,w1,w2,b1);
input i1;
input i2;
input w1;
input w2;
input b1;
output h1;
wire[0:63] i1;
wire[0:63] i2;
wire[0:63] h1;
wire[0:63] w1;
wire[0:63] w2;
wire[0:63] b1;
assign h1 = 1/(1+ 2.718281828459**((-1.0)*(i1 * w1 + i2 * w2 + b1)));
endmodule
module test1_tb();
reg[0:63] i1;
reg[0:63] i2;
reg[0:63] w1;
reg[0:63] w2;
reg[0:63] b1;
wire[0:63] h1;
initial
begin
assign i1 = 0.05;
assign i2 = 0.10;
assign w1 = 0.15;
assign w2 = 0.20;
assign b1 = 0.35;
$monitor("i1=%f, i2=%f, w1=%f, w2=%f, b1=%f, h1=%f",i1,i2,w1,w2,b1,h1);
end
test1 n1(i1,i2,h1,w1,w2,b1);
endmodule
For this program I get the output:
# i1=0.000000, i2=0.000000, w1=0.000000, w2=0.000000, b1=0.000000, h1=1.000000
It seems the module does not get the initial values in the second program. But all I did was adding few more input lines to the first program and changing the calculation.
Right now I don't know what's the error with this. Please help.
The type reg is not designed to implicitly handle floating point math. As such, real constants assigned to the reg variables are rounded to the nearest integer (see IEEE1800-2012 Section 5.7.2, SystemVerilog LRM; sorry I dont have IEEE1364, Verilog LRM, to find the reference in there).
If you simply want to do some floating point math, you can use the real type which is the same as a double. Otherwise, if you want to do floating point math in hardware, youll need to deal with the complexities of it yourself (or borrow from an IP core). Also note that Verilog is not a scripting language, but a Hardware Descriptive Language, so unless you are trying to design hardware, you are much better off using Python, Ruby or Perl for general purpose stuff.
I'm a beginner at vhdl and I'm trying to make a 8 bit divider using shift and subtract method. The code for the divider is okay, I guess, but I'm having problems in simulating the inputs. When I use the Verilog test fixture, my inputs which should be (dividend=51 [00110011b], divisor=19 [00010011b]) always end up becoming (dividend=49 [00110001b], divisor=49 [00110001b])) in iSim, and then the outputs (Quotient and remainder = xxxxxxx (unknown)) instead of (quotient=2[00000010b] and remainder=13 [00001101b])...
As I mentioned before, I'm a beginner at vhdl and I've been at this for five hours, I've tried my best to search for a solution online, but failed.... so any help or alternative solution would be greatly appreciated.
I'm using Xilinx ISE 14.3 and iSim.
Here is the code for the 8 bit binary divider.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;
entity division is
generic(SIZE: INTEGER := 8);
port(reset: in STD_LOGIC; --reset
en: in STD_LOGIC; --enable
clk: in STD_LOGIC; --clock
num: in STD_LOGIC_VECTOR((SIZE - 1) downto 0); --dividend
den: in STD_LOGIC_VECTOR((SIZE - 1) downto 0); --divisor
res: out STD_LOGIC_VECTOR((SIZE - 1) downto 0); --result/quotient
rm: out STD_LOGIC_VECTOR((SIZE - 1) downto 0) --remainder
);
end division;
architecture behav of division is
signal bufreg: STD_LOGIC_VECTOR((2 * SIZE - 1) downto 0); --signal array to hold both accumulator and dividend registers as one i.e bufreg(18 bits)
signal dbuf: STD_LOGIC_VECTOR((SIZE - 1) downto 0); --signal array to hold the divisor
signal count: INTEGER range 0 to SIZE; --count to determine when to stop
alias ADreg is bufreg((2 * SIZE - 1) downto SIZE); --ADreg is is alias for top half of bufreg register(17th to 9th bit)
alias DVNDreg is bufreg((SIZE - 1) downto 0); --DVNDreg is is alias for bottom half of bufreg register(8th to 0th bit)
begin
--our process begins here
p_001: process(reset, en, clk)
begin
if reset = '1' then
res <= (others => '0');
rm <= (others => '0');
count <= 0;
elsif rising_edge(clk) then
if en = '1' then
case count is
when 0 =>
ADreg <= (others => '0');
DVNDreg <= num;
dbuf <= den;
res <= DVNDreg;
rm <= ADreg;
count <= count + 1;
when others =>
if bufreg((2 * SIZE - 2) downto (SIZE - 1)) >= dbuf then
ADreg <= '0' & (bufreg((2 * SIZE - 3) downto (SIZE - 1)) - dbuf((SIZE - 2) downto 0));
DVNDreg <= DVNDreg ((SIZE - 2) downto 0) & '1';
else
bufreg <= bufreg((2 * SIZE - 2) downto 0) & '0';
end if;
if count /= SIZE then
count <= count + 1;
else
count <= 0;
end if;
end case;
end if;
end if;
end process;
end behav;
And here is the code for the Verilog test fixture (.v file):
module BINdivisionTEST;
// Inputs
reg reset;
reg en;
reg clk;
reg [7:0] num ;
reg [7:0] den ;
// Outputs
wire [7:0] res;
wire [7:0] rm;
// Instantiate the Unit Under Test (UUT)
division uut (
.reset(reset),
.en(en),
.clk(clk),
.num(num),
.den(den),
.res(res),
.rm(rm)
);
initial begin
// Initialize Inputs
reset = 0;
en = 0;
clk = 0;
//num = 0;
//den = 0;
// Wait 100 ns for global reset to finish
#100;
en = 1;
#100;
clk=1;
num <= "00110011" ;
den <= "00010011" ;
// Add stimulus here
end
endmodule
My biggest problems seem to be initialization of the inputs and probably some mistaken assignments, misuse of the test fixture file and some bad coding.
I should also add that the divider code was compiled in vhdl, ISE 14.3.
I'm extremely sorry if this has been answered before and I don't mean to piss anyone off by uploading bad and amateur code. If this kind of problem has been addressed before could you please provide me with a link.
Again, any help is greatly appreciated.
The simulator may be treating those as strings instead of numbers. Try changing:
num <= "00110011" ;
den <= "00010011" ;
to:
num <= 8'b00110011;
den <= 8'b00010011;
I'm no expert on Verilog but it looks as if you might not be asserting Reset to your VHDL component before testing it.
That would lead "Count" in an uninitialised state so that when you use it, anything could happen and the "XXXX" outputs are a reflection of that.
The reset sequence should look like
En <= '0';
Clk <= '0';
Reset <= '1';
wait for 100 ns;
Reset <= '0';
wait for 100 ns;
-- start testing here
(in VHDL of course ... but it'll translate to Verilog easily)
I'm trying to write the test bench for my ALU but. I'm not sure if its written in a way that makes it work. For instance, should I use dut or uut? Have I initialized my inputs correctly? The output wave is just straight (doesn't change with each bit X's and one 0).
module Alu_test();
reg [7:0]pc;
reg [3:0] CCRin;
reg rst,clk;
reg [3:0] opcode;
reg[7:0] ra;
reg[7:0] rb;
reg [7:0] in_port;
reg[7:0] SP; //= 255
wire[7:0] SP_out;
wire [7:0] out_port;
wire[255:0] dmem;
wire[7:0] ra_out;
wire[7:0] rb_out;
wire [3:0] CCRo;
wire [7:0] npc;
ALU dut(opcode,ra,rb,ra_out,rb_out,rst,clk,pc,npc,CCRin,CCRo,SP,SP_out,in_port,out_port,dmem);
initial
begin
rst = 0;
clk = 0;
opcode = 0;
SP = 255;
CCRin = 0;
pc = 0;
in_port = 0;
ra = 0;
rb = 0;
#5
forever
#5 clk = ~clk;
#50
#5 opcode[3:0] = 4'b0000; //nop
#5 opcode[3:0] = 4'b0100; //add
ra =1;
rb =1;
#5 opcode[3:0] = 4'b0111; //shift left
ra =1;
rb =0;
#5 opcode[3:0] = 4'b1010; //push
ra =1;
rb =2;
end
endmodule
this is the module
module ALU(opcode,ra,rb,ra_out,rb_out,rst,clk,pc,npc,CCRin,CCRo,SP,SP_out,in_port,out_port,dmem);
wire [7:0] res; // result
input wire [7:0]pc;
output reg [7:0] npc;
input rst,clk;
input wire [3:0] opcode;
input wire[7:0] ra;
input wire[7:0] rb;
output reg[7:0] ra_out;
output reg[7:0] rb_out;
input wire[7:0] SP; // testbench haygebli SP el mafroud yeb2a = 255
output reg[7:0] SP_out;
input wire [7:0] in_port;
output reg [7:0] out_port;
output reg[255:0] dmem;
input wire [3:0] CCRin;
output reg [3:0] CCRo;
wire co;
wire cin;
wire [7:0] result; //total result
always #(posedge clk)
begin
SP_out = SP;
end
assign result = alu_out(ra,rb,cin);
assign res = result[1:0];
assign co = result[2];
function [8:0] alu_out;
input [1:0] ra,rb;
input cin;
case (opcode)
0: ;
4: assign alu_out = ra + rb;
5: assign alu_out = ra - rb;
6: assign alu_out = ~(ra & rb);
7: assign alu_out = {ra[7:0],cin};
8: assign alu_out = {ra[0],cin,ra[7:1]};
10: if (ra == 1)
begin
dmem[SP_out] = rb;
SP_out = SP_out-1;
end
else
begin
SP_out = SP_out +1;
rb_out = dmem[SP_out];
end
11: assign out_port = ra;
12: assign ra_out = in_port;
13: assign ra_out = rb;
default: begin
alu_out = 8'bxxxxxxxx;
end
endcase
endfunction
always#(posedge clk)
begin
if (res == 0)
CCRo[0] = 1;
else if ( res < 0)
CCRo[1] = 1;
else if (co == 1)
CCRo[2] = 1;
else if ( res < 0 & res > result)
CCRo[3] = 1;
else
CCRo = CCRin;
if (res)
ra_out = res;
npc = pc+1;
end
endmodule
Using dut as the instance name is fine. You can also use uut instead, if you prefer.
You should move the clock generation into its own initial block, then call $finish at the end of your original initial block. This should get you further. Now, 4 signals become known:
initial begin
rst = 0;
opcode = 0;
SP = 255;
CCRin = 0;
pc = 0;
in_port = 0;
ra = 0;
rb = 0;
#5;
#50;
#5 opcode[3:0] = 4'b0000; //nop
#5 opcode[3:0] = 4'b0100; //add
ra =1;
rb =1;
#5 opcode[3:0] = 4'b0111; //shift left
ra =1;
rb =0;
#5 opcode[3:0] = 4'b1010; //push
ra =1;
rb =2;
$finish;
end
initial begin
clk = 0;
forever #5 clk = ~clk;
end
Your dmem initializes to X. You need to drive in opcode=10 to set it to another value.