PIC18F67K22 TX pin low after UART enable - uart

Question

I using PIC18F67K22 with MPLAB8.92 and ICD3. I set port registers for UART RC7-input and RC6-output. I then set the UART 1 for comms. The Tx Pin should go high after setting UART but stays low. When I send a byte the Tx sends data and goes high after byte sent. I have played with the BAUDCON(5)(4) but no luck. Is it possible to force the Tx pin to go high without sending a byte ? All the data on the TX pin is correct after the first byte is sent.
;// Zeta
movlw b'10010000' ;
MOVWF TRISC ;
banksel TXSTA1
movlw b'10000000' ;//
movwf TXSTA1
bsf BAUDCON1,3 ;// 16 byte
movlw .207 ;// 64 mhz
movwf SPBRG1
movlw .0
movwf SPBRGH1
movlw b'10010000'
movwf RCSTA1 ;//Enable Serial
bsf PIE1,5

Answer 1

Before the UART is enabled use the TRISC and LATC registers to configure RC6 as an output and set the output state to one.
;
; Make the UART TX output a one.
;
BANKSEL LATC
BSF LATC,6 ; Make RC6 a 1
BANKSEL TRISC
BCF TRISC,6 ; Make RC6 an output
;
; Now configure the UART and enable the TX
;
EDIT 1
This is a complete program that initializes the PIC and UART1:
list n=0,c=250 ; Make list file pretty
list r=dec ; Use decimal as the default radix
;
; File: main.asm
; Author: dan1138
; Target: PIC18F67K22
; Compiler: MPASMWIN v5.51
; IDE: MPLAB v8.92
;
;
; PIC18F67K22
; +----------+ +----------+ +-----------+ +----------+
; <> 1 : RE1 : <> 17 : RF1 : <> 33 : RC2 : <> 49 : RD7 :
; <> 2 : RE0 : -> 18 : ENVREG : <> 34 : RC3 : <> 50 : RD6 :
; <> 3 : RG0 : 5V0 -> 19 : AVDD : <> 35 : RC4 : <> 51 : RD5 :
; <> 4 : RG1 : GND -> 20 : AVSS : <> 36 : RC5 : <> 52 : RD4 :
; <> 5 : RG2 : <> 21 : RA3 : PGD <> 37 : RB7/PGD : <> 53 : RD3 :
; <> 6 : RG3 : <> 22 : RA2 : 5V0 -> 38 : VDD : <> 54 : RD2 :
; VPP -> 7 : RG5/MCLRn: <> 23 : RA1 : <> 39 : OSC1/RA7 : <> 55 : RD1 :
; <> 8 : RG4 : <> 24 : RA0 : <> 40 : OSC2/RA6 : GND -> 56 : VSS :
; GND -> 9 : VSS : GND -> 25 : VSS : GND -> 41 : VSS : 5V0 -> 57 : VDD :
; 10uF -> 10 : VCAP : 5V0 -> 26 : VDD : PGC <> 42 : RB6/PGC : <> 58 : RD0 :
; <> 11 : RF7 : <> 27 : RA5 : <> 43 : RB5 : <> 59 : RE7 :
; <> 12 : RF6 : <> 28 : RA4 : <> 44 : RB4 : <> 60 : RE6 :
; <> 13 : RF5 : <> 29 : RC1 : <> 45 : RB3 : <> 61 : RE5 :
; <> 14 : RF4 : <> 30 : RC0 : <> 46 : RB2 : <> 62 : RE4 :
; <> 15 : RF3 : <> 31 : RC6/TX : <> 47 : RB1 : <> 63 : RE3 :
; <> 16 : RF2 : <> 32 : RC7/RX : <> 48 : RB0 : <> 64 : RE2 :
; +----------+ +----------+ +-----------+ +----------+
; TQFP-64
;
INCLUDE "p18f67k22.inc"
; CONFIG1L
CONFIG RETEN = ON ; VREG Sleep Enable bit (Enabled)
CONFIG INTOSCSEL = HIGH ; LF-INTOSC Low-power Enable bit (LF-INTOSC in High-power mode during Sleep)
CONFIG SOSCSEL = HIGH ; SOSC Power Selection and mode Configuration bits (High Power SOSC circuit selected)
CONFIG XINST = OFF ; Extended Instruction Set (Disabled)
; CONFIG1H
CONFIG FOSC = INTIO2 ; Oscillator (Internal RC oscillator)
CONFIG PLLCFG = OFF ; PLL x4 Enable bit (Disabled)
CONFIG FCMEN = OFF ; Fail-Safe Clock Monitor (Disabled)
CONFIG IESO = OFF ; Internal External Oscillator Switch Over Mode (Disabled)
; CONFIG2L
CONFIG PWRTEN = OFF ; Power Up Timer (Disabled)
CONFIG BOREN = OFF ; Brown Out Detect (Disabled in hardware, SBOREN disabled)
CONFIG BORV = 3 ; Brown-out Reset Voltage bits (1.8V)
CONFIG BORPWR = ZPBORMV ; BORMV Power level (ZPBORMV instead of BORMV is selected)
; CONFIG2H
CONFIG WDTEN = OFF ; Watchdog Timer (WDT disabled in hardware; SWDTEN bit disabled)
CONFIG WDTPS = 1048576 ; Watchdog Postscaler (1:1048576)
; CONFIG3L
CONFIG RTCOSC = SOSCREF ; RTCC Clock Select (RTCC uses SOSC)
; CONFIG3H
CONFIG CCP2MX = PORTC ; CCP2 Mux (RC1)
CONFIG MSSPMSK = MSK7 ; MSSP address masking (7 Bit address masking mode)
CONFIG MCLRE = ON ; Master Clear Enable (MCLR Enabled, RG5 Disabled)
; CONFIG4L
CONFIG STVREN = ON ; Stack Overflow Reset (Enabled)
CONFIG BBSIZ = BB2K ; Boot Block Size (2K word Boot Block size)
; CONFIG5L
CONFIG CP0 = OFF ; Code Protect 00800-03FFF (Disabled)
CONFIG CP1 = OFF ; Code Protect 04000-07FFF (Disabled)
CONFIG CP2 = OFF ; Code Protect 08000-0BFFF (Disabled)
CONFIG CP3 = OFF ; Code Protect 0C000-0FFFF (Disabled)
CONFIG CP4 = OFF ; Code Protect 10000-13FFF (Disabled)
CONFIG CP5 = OFF ; Code Protect 14000-17FFF (Disabled)
CONFIG CP6 = OFF ; Code Protect 18000-1BFFF (Disabled)
CONFIG CP7 = OFF ; Code Protect 1C000-1FFFF (Disabled)
; CONFIG5H
CONFIG CPB = OFF ; Code Protect Boot (Disabled)
CONFIG CPD = OFF ; Data EE Read Protect (Disabled)
; CONFIG6L
CONFIG WRT0 = OFF ; Table Write Protect 00800-03FFF (Disabled)
CONFIG WRT1 = OFF ; Table Write Protect 04000-07FFF (Disabled)
CONFIG WRT2 = OFF ; Table Write Protect 08000-0BFFF (Disabled)
CONFIG WRT3 = OFF ; Table Write Protect 0C000-0FFFF (Disabled)
CONFIG WRT4 = OFF ; Table Write Protect 10000-13FFF (Disabled)
CONFIG WRT5 = OFF ; Table Write Protect 14000-17FFF (Disabled)
CONFIG WRT6 = OFF ; Table Write Protect 18000-1BFFF (Disabled)
CONFIG WRT7 = OFF ; Table Write Protect 1C000-1FFFF (Disabled)
; CONFIG6H
CONFIG WRTC = OFF ; Config. Write Protect (Disabled)
CONFIG WRTB = OFF ; Table Write Protect Boot (Disabled)
CONFIG WRTD = OFF ; Data EE Write Protect (Disabled)
; CONFIG7L
CONFIG EBRT0 = OFF ; Table Read Protect 00800-03FFF (Disabled)
CONFIG EBRT1 = OFF ; Table Read Protect 04000-07FFF (Disabled)
CONFIG EBRT2 = OFF ; Table Read Protect 08000-0BFFF (Disabled)
CONFIG EBRT3 = OFF ; Table Read Protect 0C000-0FFFF (Disabled)
CONFIG EBRT4 = OFF ; Table Read Protect 10000-13FFF (Disabled)
CONFIG EBRT5 = OFF ; Table Read Protect 14000-17FFF (Disabled)
CONFIG EBRT6 = OFF ; Table Read Protect 18000-1BFFF (Disabled)
CONFIG EBRT7 = OFF ; Table Read Protect 1C000-1FFFF (Disabled)
; CONFIG7H
CONFIG EBRTB = OFF ; Table Read Protect Boot (Disabled)
;
; Define what we want the system clock frequency
; to be set to by the initialzation code.
;
#define FSYS (8000000)
#define FCYC (FSYS/4)
#define BAUD (9600)
#define BRG_VALUE (FSYS/BAUD)/4-1
;*******************************************************************************
; Reset Vector
;*******************************************************************************
RES_VECT CODE 0x0000 ; processor reset vector
GOTO START ; go to beginning of program
;*******************************************************************************
; MAIN PROGRAM
;*******************************************************************************
MAIN_PROG CODE ; let linker place main program
START
BSF LATC,6 ; Make TX output high
BCF TRISC,6 ; Turn on output driver
CLRF RCSTA1 ; Disable UART1
CLRF TXSTA1
CLRF BAUDCON1
BSF BAUDCON1,BRG16 ; Use 16-bit baud rate generator
BSF TXSTA1,BRGH ; Select high speed baud rate generator
BSF TXSTA1,TXEN ; Enable transmitter
BSF RCSTA1,CREN ; Enable reciever
MOVLW LOW(BRG_VALUE)
MOVWF SPBRG1
MOVLW HIGH(BRG_VALUE)
MOVWF SPBRGH1
BSF RCSTA1,SPEN ; Enable UART1
;
; With an 8MHz system clock this is about a
; 100ms wait for UART1 hardware to be ready.
;
MOVLW 0
CLRF PRODL
UART1_SpinWait:
DECFSZ PRODL,F
BRA UART1_SpinWait
DECFSZ WREG,F
BRA UART1_SpinWait
MOVLW '>'
CALL UART1_SendByte
GOTO $ ; loop forever
;
; Send a byte to UART1
;
UART1_SendByte:
BTFSS TXSTA1,TRMT ; Skip when transmitter is empty
BRA UART1_SendByte
MOVWF TXREG
RETURN
END
See how this works in your hardware.