vhdl loop must terminate within 10,000 iteration error despite having a count to 1000 - while-loop

Question

My task is to create a GCD calculator using a state machine in VHDL. Part of the task description says to use a while loop while(tempA /= tempB). When I used this loop I get following compilation error:
Error (10536): VHDL Loop Statement error at GCD_FSM.vhd(64): loop must terminate within 10,000 iterations
After doing some research online, I tried to fix this by implementing a count variable: loop_count, which increments on each iteration upto 10,000. Initially I still got the same error so tried reducing the max count value to only 1,000, which is the current set up in my code below.
For some reason that I cant understand I still get the same error, does anyone know why this is or have a solution? I am using Quartus II 13.1 as that is the latest edition with Cyclone III which is what we use at uni.
-- output function
process(current_state)
variable loop_count : integer range 0 to 10000 := 0;
begin
if current_state = STATE_load then
tempA <= unsigned(A);
tempB <= unsigned(B);
elsif current_state = STATE_calculate then
while (tempA /= tempB and loop_count < 1000) loop
if tempA < tempB then
tempB <= tempA - tempB;
else
tempA <= tempA - tempB;
end if;
loop_count := loop_count + 1;
end loop;
elsif current_state = STATE_done then
GCD <= std_logic_vector(tempA);
DONE <= '1';
end if;
end process;
Updating to add the full code for context below:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use ieee.std_logic_unsigned.all;
entity GCD_FSM is
port(
A, B : in std_logic_vector(15 downto 0);
CLK, RESET, START : in std_logic;
GCD : out std_logic_vector(15 downto 0);
DONE : inout std_logic
);
end entity GCD_FSM;
architecture moore_machine of GCD_FSM is
type STATE is (
STATE_idle, STATE_load,
STATE_calculate, STATE_done
);
signal current_state, next_state : STATE;
signal tempA, tempB : unsigned(15 downto 0) := (others => '0');
begin
-- next state fuction
process(A, B, current_state)
begin
case current_state is
when STATE_idle =>
if START = '1' then
if (unsigned(A) /= 0) and (unsigned(B) /= 0) then
next_state <= STATE_load;
end if;
end if;
when STATE_load =>
next_state <= STATE_calculate;
when STATE_calculate =>
if tempA = tempB then
next_state <= STATE_done;
end if;
when STATE_done =>
next_state <= STATE_idle;
end case;
end process;
-- state register
process(CLK, RESET)
begin
if RESET = '0' then
current_state <= STATE_idle;
elsif rising_edge(CLK) then
current_state <= next_state;
end if;
end process;
-- output function
process(current_state)
variable loop_count : integer range 0 to 10000 := 0;
begin
if current_state = STATE_load then
tempA <= unsigned(A);
tempB <= unsigned(B);
elsif current_state = STATE_calculate then
while (tempA /= tempB and loop_count < 1000) loop
if tempA < tempB then
tempB <= tempA - tempB;
else
tempA <= tempA - tempB;
end if;
loop_count := loop_count + 1;
end loop;
elsif current_state = STATE_done then
GCD <= std_logic_vector(tempA);
DONE <= '1';
end if;
end process;
end architecture moore_machine;