Cause of gated clock - hardware

Question

I have this code in VHDL. When I try to compile it - it says "Gated clock net clock_en is sourced by a combinatorial pin." Has anyone an idea how to get rid of this warning?
I have searched all over the internet and cant find the solution. It seems that gated clock is sometimes even useful, but when designing HW it is a warning.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity ledc8x8 is
port(
SMCLK: in std_logic;
RESET: in std_logic;
ROW: out std_logic_vector(0 to 7);
LED: out std_logic_vector(0 to 7)
);
end ledc8x8;
architecture behavioral of ledc8x8 is
signal count: std_logic_vector(7 downto 0) := (others => '0'); -- hlavni citac
signal row_count: std_logic_vector(7 downto 0) := "10000000"; -- prepinac radku
signal clock_en: std_logic; -- CE
signal output_logic: std_logic_vector(7 downto 0); -- "vystup"
begin
process(count, SMCLK, RESET, clock_en)
begin
if RESET = '1' then
count <= (others => '0');
elsif SMCLK = '1' and SMCLK'event then
count <= count + 1;
end if;
if count="11111110" then
clock_en <= '1'; else
clock_en <= '0';
end if ;
end process;
process(clock_en, RESET)
begin
if RESET = '1' then
row_count <= "10000000";
elsif clock_en = '1' and clock_en'event then
row_count <= row_count(0) & row_count(7 downto 1);
end if;
end process;
process(row_count)
begin
case row_count is
when "00000001" => output_logic <= "11110110";
-- more switch options
end case;
end process;
ROW <= row_count;
LED <= output_logic;
end behavioral;

Answer 1

Your code has several problems.
As you discovered in your answer, you were using a clock enable as a clock. I would recommend that you write it this way, though:
process(RESET, SMCLK)
begin
if RESET = '1' then
row_count <= "10000000";
elsif SMCLK = '1' and SMCLK'event then
if clock_en = '1' then
row_count <= row_count(0) & row_count(7 downto 1);
end if;
end if;
end process;
It may work the other way (maybe), but it's not conventional to put the enable check on the same line as the rising edge check. Note also that this means you don't need clock_en in your sensitivity list.
Your other clocked process should be rewritten as well. Assuming you want the assignment to clock_en to be combinational, you should really put it in a separate process:
process(RESET, SMCLK)
begin
if RESET = '1' then
count <= (others => '0');
elsif SMCLK = '1' and SMCLK'event then
count <= count + 1;
end if;
end process;
process (count)
begin
if count="11111110" then
clock_en <= '1';
else
clock_en <= '0';
end if ;
end process;
You could also write the second process here as a one-line concurrent statement:
clock_en <= '1' when count = "11111110" else '0';
Combining independent clocked and unclocked code in the same process is not a recommended coding style for various reasons.

Answer 2

The line with clock_en'event - asking for rising edge did the problem. Replaced to ask for rising edge of SMCLK signal.
process(RESET, SMCLK)
begin
if RESET = '1' then
row_count <= "10000000";
elsif clock_en = '1' and SMCLK = '1' and SMCLK'event then
row_count <= row_count(0) & row_count(7 downto 1);
end if;
end if;
end process;