I Need to communicate my EFM32LG with a dac80004 USING SPI.
When i define USART in SPI mode i need to define the pins and ports as follwoing:
Port A pin 2: chip select sync_not (active low)
Port E pin 10: MOSI (SDIN)
Port E pin 11: MISO (serial interface digital out)
Port E pin 12: SCLK
Port A pin 1: clear DAC pin
From the API shown in the link bellow,I have only _USART_ROUTE_LOCATION_LOC0 .
How do i Put set my actual locations Using the API of SPIDRV?
Thanks.\
https://docs.silabs.com/mcu/latest/efm32lg/group-SPIDRV#gaec2cac185e42ded3da0d3e2d5cd56226
The values listed there are the defaults, they're not the only option.
If you look at the EFM32LG datasheet, page 352 there are other locations where you can set up the USART0 SPI pins.
Location 0 is fine for MOSI, MISO and CLK, but the CS would need to be PE13 if you want it driver controlled.
Alternatively, you could alter spidrvCsControlAuto to spidrvCsControlApplication and control the CS manually as a GPIO.
Related
TMP102 chip( http://www.ti.com/lit/ds/symlink/tmp102.pdf ) can have multiple I2c slave addresses. It has an address pin called ADD0(Section 5) which can be used to select multiple addresses(Section 7.3.4). The logic level at that pin can be used to select a particular TMP102 slave device. According to table 4, 4 addresses are possible. I do understand that connecting the pin to high or low voltage will produce two different addresses. But the table mentions that we can use SDA and SCL pins for two different addresses. I am not sure how this works. Can anyone explain how can this be used and how can we use multiple TMP102 devices based on SDA and SCL pins.
The logic level at that pin can be used to select a particular TMP102 slave device
That is not the purpose of ADD0 - it is a configuration pin, not a select pin. It is not used to select the device; I2C addresses are part of the data stream on SDA, there is no "select" pin as there is on SPI for example.
Rather, ADD0 is used to define the address of each device to one of four defined in Table 4. Those addresses being one of 0x48, 0x49, 0x4A or 0x4B depending on connection of ADD0 to GND, V+, SDA or SDL respectively. Like so:
How the device determines the address is not revealed in the datasheet and you don't really need to know, but given:
Public domain image by Marcin Floryan from https://en.wikipedia.org/wiki/I%C2%B2C
at the start condition at the falling edge of SDA the following occurs:
ADDR ADD0 SDA SCL
0x48 0 v 1
0x49 1 v 1
0x4A v v 1
0x4B 1 v 1
Then on the next falling edge SCL
ADDR ADD0 SDA SCL
0x48 0 0 v
0x49 1 0 v
0x4A 0 0 v
0x4B v 0 v
So it is possible with suitable sequential logic to latch the address by the end of the S phase and before B1 which is sufficient because the address match does not occur until B7, and all devices on the bus must listen for the address.
You connect ADD0 to SDA/SCL to get those other addresses. The table shows the address you get based on what ADD0 is connected to.
I would provide din+ to A1 and din- to A2, on pin connector on PM2 module, connecting to FPGA, but I have only 1 input port "din" in top level vhdl design module connected to AG7 pin on FPGA. How to go about connection in UCF file ?
PM2 Pin - A1, A2
FPGA pin -AG7, AG6
FPGA bank VCCO - 2.5v, 2.5v
Pin Function - LVDS pair 100 ohm differential impedance; can also be used as single-ended
You have to manually instantiate the differential input buffer. For Xilinx it will be IBUFDS in the Unisim library. Either modify your port to have two pins for din and add the buffer in the existing design or write a simple wrapper that converts the diff. pairs to single-ended and pass that into the current port.
I am new to Stellaris LM3S8962. I want to inquire about how to write 4 separate ISRs to handle interrupts originated from 4 buttons Up, Down, Left, Right. I have tried but my code always fell into FaultISR.
Thanks!
https://www.dropbox.com/s/5j5il9kt324o943/Lab%202.rar?dl=0
The link above is my project.
It works fine, but when I add the following statements to the Startup task it would fall into FaultISR
// Configure the UART
SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
// Enable processor interrupts.
IntMasterEnable();
// Set GPIO A0 and A1 as UART pins.
GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1);
// Configure the UART for 9600, 8-N-1 operation.
UARTConfigSetExpClk(UART0_BASE, SysCtlClockGet(), 9600,
(UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE |
UART_CONFIG_PAR_NONE));
// Enable the UART interrupt.
IntEnable(INT_UART0);
UARTIntEnable(UART0_BASE, UART_INT_RX | UART_INT_RT);
i am using a A20 OLinuXino Micro 4GB from Olimex with Debian on SD Card.
I want to use the GPIOs and have some short question about the configuration of the GPIOs. The GPIO-1 connector on the board has pins numbered from 1 to 39. In the manual I have entries like that:
Pin # | Signal name | Processor pin
23 | PG9 | C19
...
39 | LRADC1 | AB22
In the fex file, I find this:
[gpio_para]
gpio_used = 1
gpio_num = 64
...
gpio_pin_10 = port:PG09<0><default><default><default>
How is defined that the processor pin C19 is routed to port PG9?
And port means exactly what?
How is defined that the port PG9 is routed to pin23 of the connector?
Can the gpio_pin_10 designation be chosen arbitrarily?
At the end I would like to use the LRADC1, to sample a signal, but the fex file doesn't have any LRADC1 entry. Why is that?
Maybe somebody could answer may questions in 2 or 3 sentences so it makes sense to the rest of what I read. Thanks!
Please take a look at A20-OLinuXino-MICRO schematics. You can find wiring:
PG09 - C19
PG10 - D18
PG11 - C18
(...)
In mentioned schematics is also section GPIO EXTENSION in which you can find which A20 SoC pin is assigned to which GPIO:
PG09 - 23 GPIO-1
PG10 - 25 GPIO-1
According to Wikipedia:
A GPIO port is a group of GPIO pins (typically 8 GPIO pins) arranged in a group and controlled as a group.
Mapping between physical pin and pin exposed through fex file to operating system is arbitrary. Of course to get correct results you have to assign GPIO ping not. I don't think that fex compiler check anything other then syntax.
In case LRADC0 (again schematics) it us used for buttons (vol +/-, menu, search, ...) and LRADC1 is exposed through GPIO-1 pin 39.
I am trying to use UP501 gps module on Arduino and get a raw information from the GPS like long, lat,alt..etc
I am running this code on Arduino to see if the serial on GPS is available, if it is then print out the data from GPS.
Arduino Code:
#include <SoftwareSerial.h>
SoftwareSerial mySerial(10, 11); // RX, TX .
void setup()
{
// Open serial communications and wait for port to open:
Serial.begin(57600);
Serial.println("Searching using GPS...");
// set the data rate for the SoftwareSerial port
mySerial.begin(9600);
}
void loop() // run over and over
{
if (mySerial.available())
Serial.write(mySerial.read());
}
My problem: I don't get any data from the GPS module.
I thought it would be from the wiring. See the picture below of my wiring.
yellow wire from pin 2 is connected to D10 which will be the RX
black wire from pin 3 is connected to ground.
Red wire from pin 4 is connected to 3.3 volts
Note: I went outside(outdoor) to get a satellite but no information
There is a tutorial on adafruit for using this gps
I sugest you take a look at it becuse your wireing seems to be missing a few things