The Fmax parameter in my code was reported as : No Paths to report. Therefore, I was trying to set input signal relationship with the defined clock using set_input_delay. However, the error report states:
Verilog HDL Syntax error near text "-" ; expecting "." or "(".
I checked the documentation on the Intel website, and it shows that the correct syntax is:
set_input_delay -clock clk 1.5 [get_ports myin]
module DT2(a,b,c,f,e,g,newin,v,w,x,m,n,F1,r,N1,D1,p,q,j,n1,t,clk,new);
input clk;
input [10:0]new;
set_input_delay -clock clk 1.5 [get_ports new];
output reg [12:0]a;
output reg [11:0]b;
output reg [10:0]c,f,e,g,m,n,F1,r;
output reg [10:0]newin;
output reg [40:0]v;
output reg [30:0]w;
output reg [20:0]x,N1,D1,p,q,n1;
output reg [1:0]j;
output reg t;
integer i;
initial
begin
a=13'b100_1000011111; //3.10
b=12'b10_1110011110; // 2.10
c=11'b1_0000101010; //1.10
e=11'b0_0000100100; //1.10
f=11'b0_0010111100; //1.10
g=11'b0_0111000000; //1.10
end
always # (posedge clk)
begin
newin=new;
t=newin[10];
if(t==1'b1)
begin
newin=newin-11'b1_0000000000;
v = (newin*newin*newin*e);
w = (newin*newin*f);
x = (newin*g);
m=(v[40:30])+(x[20:10])+(11'b0_0000000101);
n = m-(w[30:20]);
x=(n*n);
n=n<<1;
m=n-x[20:10]; //need to keep
n=n>>1;
n=(11'b1_0000000000)-n;
end
else
begin
v = (newin*newin*newin*a);
w = (newin*newin*b);
x = (newin*c);
m=(v[40:30])+(x[20:10])+(11'b0_0000001100);
n = m-(w[30:20]);
x=(n*n);
n=n<<1;
m=n+x[20:10]; //need to keep
n=n>>1;
n=(11'b1_0000000000)+n;
end
n1=(n*n);
//SHIFTING NONE
j=2'b00;
for(i=0;i<=16;i=i+1)
begin
if(j==2'b00)
begin
N1=m*(n1[20:10]);
D1=(n1[20:10])*(n1[20:10]);
F1=12'b10_0000000000-D1[20:10];
j=2'b01;
end
else if(j==2'b01)
begin
p=F1*N1[20:10];
q=F1*D1[20:10];
r=12'b10_0000000000-D1[20:10];
j=2'b10;
end
else if(j==2'b10)
begin
N1=r*p[20:10];
D1=r*q[20:10];
F1=12'b10_0000000000-D1[20:10];
j=2'b01;
end
end
end
endmodule
You must remove the following line from your Verilog code because it is not legal Verilog syntax:
set_input_delay -clock clk 1.5 [get_ports new];
It looks like a command for your synthesis tool, and it likely belongs in a synthesis script.
The statement set_input_delay -clock clk 1.5 [get_ports myin] as has been already stated, is not Verilog. It is a Synopsis Design Constraint.
In a Quartus project, a .sdc file is used to hold the timing constraints for the design. Your statement needs to go in there. During the build process this file is an input to the synthesis tool and fitter tool.
Related
I am trying to implement BIST (Built-in self-test). Test pattern generator(TPG) module generates test patterns using LFSR per posedge clk (always #1 clk = ~clk). I am using 32 stage LFSR. Each value of TPG module is sent to the AES encryption module which gives ciphertext after #141 delay. During this #141 delay many of the TPG module outputs are lost. How to solve this problem?
I thought a solution is to store thousand test pattern values in the array (reg [127:0] arr [0:999]) and then send each test pattern to the AES encryption module. Is this a good solution because I think it is making chip memory bigger. If it is then what should I do? The code snippet is given below.
wire [127:0] state_byte;
TPG T (clk, rst, bistMode, state_byte);
AES_encryption ENC_TB(key_byte, state_byte, clk, rst, encryptionEnable, state_out_byte, load, ready);
codes of TPG module is given below:
module TPG (input wire clk, input wire rst, input wire sel, output reg[127:0] valueO);
integer i;
reg [31:0] patternGenerate[0:3],temp;
always #(posedge clk)begin
if(sel == 1)begin
if(rst)begin
valueO = 128'b0;
temp = 32'b11111111111111111111111111111111;
end
else
begin
for(i=0;i<4;i=i+1)begin
temp = {(temp[31] ^ temp[25] ^ temp[22] ^ temp[21] ^ temp[15] ^ temp[11] ^ temp[10] ^ temp[9] ^ temp[7] ^ temp[6] ^ temp[4] ^ temp[3] ^ temp[1] ^ temp[0]), temp[31:1]};
patternGenerate[i] = temp;
end
valueO = {patternGenerate[3],patternGenerate[2],patternGenerate[1],patternGenerate[0]};
end
end
end
endmodule
module accumulator (
input [7:0] A ,
input reset,
input clk,
output reg carryout,
output reg overflow,
output reg [8:0] S,
output reg HEX0,
output reg HEX1,
output reg HEX2,
output reg HEX3
);
reg signA;
reg signS;
reg [7:0] magA;
reg [7:0] magS;
reg Alarger;
initial begin
S = 9'b000000000;
end
always_ff # (posedge clk, posedge reset) begin
if (reset) begin
S = 9'b000000000;
end
else begin
begin
signA <= A[7]; //Is A negative or positive
signS <= S[7];
S <= A + S;
end
if (signA == 1) begin //A is negative so magnitude is of 2s compliment
magA <= (~A[7:0] + 1'b1);
end
else begin
magA <= A;
end
if (signS == 1) begin //sum is negative so magnitude is of 2s compliment
magS <= (~S[7:0] + 1'b1);
end
else begin
magS <= S;
end
if (magA > magS) begin
Alarger <= 1'b1; //Magnitude of A is larger than magnitude of sum
end
else begin
Alarger <= 1'b0;
end
if ((signA == 1) & (Alarger == 1) & (S[7] == 0)) begin
overflow <= 1'b1;
end
else begin
overflow <= 1'b0;
end
if ((signS == 1) & (Alarger == 0) & (S[7] == 0)) begin
overflow <= 1'b1;
end
else begin
overflow <= 1'b0;
end
if ((signS == 1) & (signA == 1) & (S[7] == 0)) begin
overflow <= 1'b1;
end
else begin
overflow <= 1'b0;
end
if ((signS == 0) & (signA == 0) & (S[7] == 1)) begin
overflow <= 1'b1;
end
else begin
overflow <= 1'b0;
end
if (S[8] == 1) begin //carryout occurred
carryout <= 1'b1;
overflow <= 1'b0;
S <= 9'b000000000; //sum no longer valid
end
else begin
carryout <= 1'b0;
end
display_hex h1 //display of A
(
.bin (magA),
.hexl (HEX2),
.hexh (HEX3)
);
display_hex h2 //display of sum
(
.bin (S[7:0]),
.hexl (HEX0),
.hexh (HEX1)
);
end
end
endmodule
I am trying to make an accumulator that adds A (8 digit binary value that can be signed or unsigned) repeatedly to the sum. Once the sum is computed, then sum and A should display the value on 4 hex display LEDs (2 LEDs for A and 2 LEDs for sum). However, I am having a hard time getting it to compile. I have searched the error code and it seems like a general error for a syntax error and can have several meanings.
The error is the result of these two lines:
display_hex h1 //display of A
(
.bin (magA),
.hexl (HEX2),
.hexh (HEX3)
);
display_hex h2 //display of sum
(
.bin (S[7:0]),
.hexl (HEX0),
.hexh (HEX1)
);
Here, it appears you have a module named display_hex which converts an 8-bit value into the needed digits for a seven segment display. You are trying to use the module as if it were a function and modules are very much NOT functions. Modules in Verilog (or SystemVerilog as you are using, but the difference is really token at this point) can be though of as a group of hardware that takes in some inputs and spits out some outputs; and its important to note that they are static things. They either exist in the design or they do not; just like using ICs on a breadboard. The top module is the breadboard and the modules you declare under that module are components you are plugging into the board. The inputs and outputs are the various connections (pins) you must wire up to make everything work.
That said, always blocks (like the always_ff you are using) form a way of describing the logic and registers inside modules. Thus, you do thinks like assign logic/reg variables inside them to describe how the hardware behaves. If you look at your logic, you'll notice that the module declarations are dependent on reset; ie if reset is asserted, these modules wont exist, which doesnt make any sense. Electrical signals don't make entire ICs in a circuit disappear! Thus, you need to pull your module declaration out of your logical description of your acculumator, like so:
module accumulator (
...
);
...
display_hex h1 //display of A
(
.bin (magA),
.hexl (HEX2),
.hexh (HEX3)
);
display_hex h2 //display of sum
(
.bin (S[7:0]),
.hexl (HEX0),
.hexh (HEX1)
);
...
always_ff #(posedge clk, posedge reset) begin
// Your accumulator logic here
...
end
endmodule
Notice that the module declarations for the display_hex modules are stand alone, as I am declaring these modules exist, not dependence on anything!
However, there are a number of issues with your design besides that:
As you are using SystemVerilog constructs (always_ff), you should declare all of your variables type logic, not reg or left blank (ie, input clk should be input logic clk, reg signA should be logic signA). The logic type just makes everything easier, so use it :)
In your always_ff block, you do reset correctly except that the assignment should really be NBA (use S <= 9'b0;, not S = 9'b0; in the if (reset))
You use NBA inside your always_ff, which is correct, however, it appears you need to use these values right away in the following logic. This will not work as you expect, or at least it will not act within the same clock cycle. To fix this, youll need to decide what should be a register and what should just be values resulting from intermediate logic, then create a separate always_comb for the intermediate values.
I am making the assumption that the HEX variables are meant for seven segment displays, so they should probably declared at least [6:0] HEXn
I was not able to reproduce the exact error, but moving the instantiations of display_hex outside always_ff resolves the main issue:
module accumulator
(
/* ... */
);
// ...
always_ff # (posedge clk, posedge reset) begin
/* ... */
end
display_hex h1 (
/* ... */
);
display_hex h2 (
/* ... */
);
endmodule
Another thing: The code drives variable S from initial as well as always. This creates multiple drivers and the code will not compile. To fix this, remove the initial completely, you don't need it since S will be set to 0 when reset is asserted.
OR
You can move all the logic into the initial block; it'd look something like this (but this, most probably, won't synthesize):
initial begin
S = 0;
forever begin
wait #(posedge clock);
// Do stuff here ..
end
end
I am trying to read a text file which contains integer numbers. I have this txt file in project folder. I am trying to use this code but it is getting char due to $fgetc. Now what I want do is that how can I get integers from text?
Here is code:
integer file;
reg [31:0] char;
begin
file=$fopen ("Links.txt","rb");
char=$fgetc(file);
$display("char=%d", char);
end
PS: This is my first time, I am reading any file.
This solution was posted previously using SystemVerilog, edited verion here for Verilog compatible syntax.
integer data_file ; // file handler
integer scan_file ; // file handler
reg [21:0] captured_data;
`define NULL 0
initial begin
data_file = $fopen("data_file.dat", "r");
if (data_file == `NULL) begin
$display("data_file handle was NULL");
$finish;
end
end
always #(posedge clk) begin
scan_file = $fscanf(data_file, "%d\n", captured_data);
if (!$feof(data_file)) begin
//use captured_data as you would any other wire or reg value;
end
end
I have created a simple module that I replicate several times using the Verilog generate statement. However, it seems that the generate statement somehow effects variable assignment in the module. Here's the code:
module test();
timeunit 10ns;
timeprecision 1ns;
wire[3:0] out;
reg[3:0] values[0:4] = {5, 6, 7, 8, 9};
logic clk;
generate
genvar i;
for (i=0; i < 5; i++) begin: M1
MUT mut(
.out,
.in(values[i]),
.clk
);
end
endgenerate
initial begin
#1 clk = 0;
$monitor("%b %b %b %b %b\n", M1[0].mut.out, M1[1].mut.out, M1[2].mut.out, M1[3].mut.out, M1[4].mut.out);
#10 $stop;
end
always #1 clk++;
endmodule
module MUT(output [3:0] out, input [3:0] in, input clk);
reg[3:0] my_reg[0:7];
assign out = my_reg[7];
always #(posedge clk) begin
my_reg[7] <= in; //5
end
endmodule
The expected output of this test program would be 0101 0110 0111 1000 1001, however the output I get is xxxx xxxx xxxx xxxx. It seems that the values in the values variable in the test module are not getting assigned to the out variable in the MUT module. However, when I replace my_reg[7] <= in; with say, my_reg[7] <= 5;, the code works as expected. The code also works when I assign directly to out (after declaring it as register) i.e. out <= in;. There's no problem if I replicate the MUT modules 'manually' without using any generate statements.
You are not connecting the outputs to separate wires. So they are implicitly tied together(like how it did for clock) resulting multiple drivers for a bit.
Just add
wire[3:0] out[0:4];
generate
genvar i;
for (i=0; i < 5; i++) begin: M1
MUT mut(
.out(out[i]), // Connect to different wires
.in(values[i]),
.clk
);
end
endgenerate
Try to initialize clk variable with 0.
Can anyone help me create a testbench or just the input code for my following code? I'm using XILINX.
module fsmb (input rst,clk,a,
output reg x);
parameter sta = 2'b00, stb = 2'b01, stc = 2'b10,
std = 2'b11;
reg[1:0] st, nst;
always #(posedge clk)
begin
if (rst)
st <= 2'b00;
else
st <= nst;
end
always #*
begin
st = nst; x =0'b0;
case (st)
sta: if(a) nst = stb;
else nst = sta;
stb: if(a) nst = stc;
else nst = stb;
stc: begin
if(a) nst = stc;
else nst = std;
x =1'b1;
end
std: begin
if(a) nst = stc;
else nst = sta;
x = 1'b1;
end
default: nst = sta;
endcase
end
endmodule
Testbench 101
Create a new module (tb).
Create a reg for each input of your DUT.
Create a wire for each output of your DUT.
Create an instance of your DUT.
Connect your regs and wires to your DUT.
Generate a clock
Drive your other inputs
Create checkers for your outputs (I'll leave this up to you).
Example:
module tb;
reg rst,clk,a;
wire x;
initial begin
clk = 0;
forever #5 clk = ~clk;
end
initial begin
rst = 1;
a = 0;
#50 rst = 0;
#50 $finish;
end
fsmb fsmb (
.clk (clk),
.rst (rst),
.a (a),
.x (x)
);
endmodule
Other simple testbench examples are provided on EDA playgound. You can sign up for a free account and look at samples such as: Published Playgounds -> D flip flop
Xilinx ISE will generate a skeleton test fixture automatically. Go to menu item Project->New Source. The dialog box will ask you to "Select Source Type" click "Verilog Test Fixture" and give it a name like testbench1 and click Next. Then it will then ask you which module in your project to associate with it. Select fsmb. Click Next and Finish.
You still have to tweak the testbench like setting the initial input values, generating a clock, and lifting reset after a few clocks.