How to resolve the delay problem between two modules in Verilog - cryptography

Question

I am trying to implement BIST (Built-in self-test). Test pattern generator(TPG) module generates test patterns using LFSR per posedge clk (always #1 clk = ~clk). I am using 32 stage LFSR. Each value of TPG module is sent to the AES encryption module which gives ciphertext after #141 delay. During this #141 delay many of the TPG module outputs are lost. How to solve this problem?
I thought a solution is to store thousand test pattern values in the array (reg [127:0] arr [0:999]) and then send each test pattern to the AES encryption module. Is this a good solution because I think it is making chip memory bigger. If it is then what should I do? The code snippet is given below.
wire [127:0] state_byte;
TPG T (clk, rst, bistMode, state_byte);
AES_encryption ENC_TB(key_byte, state_byte, clk, rst, encryptionEnable, state_out_byte, load, ready);
codes of TPG module is given below:
module TPG (input wire clk, input wire rst, input wire sel, output reg[127:0] valueO);
integer i;
reg [31:0] patternGenerate[0:3],temp;
always #(posedge clk)begin
if(sel == 1)begin
if(rst)begin
valueO = 128'b0;
temp = 32'b11111111111111111111111111111111;
end
else
begin
for(i=0;i<4;i=i+1)begin
temp = {(temp[31] ^ temp[25] ^ temp[22] ^ temp[21] ^ temp[15] ^ temp[11] ^ temp[10] ^ temp[9] ^ temp[7] ^ temp[6] ^ temp[4] ^ temp[3] ^ temp[1] ^ temp[0]), temp[31:1]};
patternGenerate[i] = temp;
end
valueO = {patternGenerate[3],patternGenerate[2],patternGenerate[1],patternGenerate[0]};
end
end
end
endmodule