Strange RTL output - yosys

Question

[Yosys 0.8]
A colleague of mine threw some random verilog code to Yosys to see how it reacts.
Here it is:
module top(input clk, input led, output led2, output to_port1,output [24:0] to_port2);
reg ctr = 0;
reg[24:0] counter = 2;
always#(posedge clk) begin
if (ctr == 1) begin
ctr <= 0;
counter <= counter + 1;
end
else
ctr <= 1;
end
assign led2 = ctr;
assign to_port1 = led;
assign to_port2 = counter;
endmodule
and Yosys, with command yosys -o synth.v x.v throws:
module top(clk, led, led2, to_port1, to_port2);
reg [24:0] _0_;
reg _1_;
reg [24:0] _2_;
reg _3_;
wire [31:0] _4_;
wire _5_;
input clk;
reg [24:0] counter;
reg ctr;
input led;
output led2;
output to_port1;
output [24:0] to_port2;
assign _4_ = counter + 32'd1;
assign _5_ = ctr == 32'd1;
always #* begin
_3_ = 1'h0;
end
always #* begin
end
always #({ }) begin
ctr <= _3_;
end
always #* begin
_2_ = 25'h0000002;
end
always #* begin
end
always #({ }) begin
counter <= _2_;
end
always #* begin
_1_ = ctr;
_0_ = counter;
casez (_5_)
1'h1:
begin
_1_ = 1'h0;
_0_ = _4_[24:0];
end
default:
_1_ = 1'h1;
endcase
end
always #(posedge clk) begin
ctr <= _1_;
counter <= _0_;
end
assign led2 = ctr;
assign to_port1 = led;
assign to_port2 = counter;
endmodule
Some constructs end up being complicated. This result code above cannot be compiled by recent verilog compilers when the original can.
Why the always #({ }) begin construct and empty always #* begin?
Is there an option we missed?
Thanks

Answer 1

In general you should always run proc (-p proc) between reading and writing Verilog, due to the nature of Yosys' internal representation of the read-in Verilog