Verilog: Sum over n register - sum

Question

Im trying to build an moving average module. It should use the number of values to use as parameter.
How do I get the sum of all n tmp-registers using a for- or gernerate-block within one clock-cylce?
reg [WORDLEN - 1:0] tmp [SIZE - 1:0];
reg [WORDLEN + SIZE / 2 - 1:0] sum;
always #(posedge clk)
sum <= sum(tmp) // Like <= tmp[0] + tmp[1] + ... + tmp[SIZE-1]

Answer 1

Loops like this tend to be easier to understand if you first break apart the synchronous and combinatorial parts. First we have a combinatorial loop which unrolls to a configurable number of adds. Then imply a flip-flop on the result.
integer i;
reg [WORDLEN + SIZE / 2 - 1:0] sum_comb;
always #* begin
sum_comb = 'd0;
for( i=0; i< SIZE; i=i+1) begin
sum_comb = sum_comb + tmp[i];
end
end
always #(posedge clk) begin
sum <= sum_comb;
end

Answer 2

If you use SystemVerilog, you can just write:
always #(posedge clk)
sum <= tmp.sum;
Below is a complete sample code:
module test;
parameter WORDLEN = 8;
parameter SIZE = 4;
reg [WORDLEN - 1:0] tmp [SIZE - 1:0];
reg [WORDLEN + SIZE / 2 - 1:0] sum;
logic clk = 0;
initial begin
tmp = '{ '{1}, '{4}, '{6}, '{7}};
forever begin
clk = ~clk;
#10;
tmp [0] = tmp[0] + 1; //Increment tmp[0] twice during each clock for testing
end
end
always #(posedge clk) begin
sum <= tmp.sum ;
$display ("sum(tmp) = sum(%p) = %d", tmp, sum) ;
end
endmodule
output:
# sum(tmp) = sum('{1, 4, 6, 7}) = 18
# sum(tmp) = sum('{1, 4, 6, 9}) = 20
# sum(tmp) = sum('{1, 4, 6, 11}) = 22
# sum(tmp) = sum('{1, 4, 6, 13}) = 24
# sum(tmp) = sum('{1, 4, 6, 15}) = 26
# sum(tmp) = sum('{1, 4, 6, 17}) = 28