I try to write the function which is determine remainder of long division algorithm Specifically, find the remainder of polynomial f on the divison by F with F is the family of polynomials. I got stuck and here is my code.
with(Groebner); LT := proc (f, order)
return LeadingCoefficient(f, order)*LeadingMonomial(f, order)
end proc
with(Groebner);
CHIA:=proc(f,Lf,order) local Lq,p,i,j,r,divisionoccurred;
for j from 1 to nops(Lf) do
Lq[j]:=0;
od;
r:=0;p:=f;
while p<>0 do
i:=1
divisionoccurred:=false
while i<=nops(Lf) and divisionoccurred=false do
if divide(LT(p,order),LT(Lf[i],order)) then
Lq[i]:=Lq[i]+(LT(p,order))/(LT(Lf[i],order));
p:=p-((LT(p,order))/(LT(Lf[i],order)))*Lf[i];
divisionoccurred:=true;
else
i:=i+1;
fi;
end do;
if divisionoccurred=false then
r:=r+LT(p,order);
p:=p-LT(p,order);
fi;
end do;
return Lq,r
end proc;
Related
I am trying to simulate the below code. However, it shows the error " found '0' definitions of operator "", cannot determine exact overloaded matching definition for "" ". I have had attached the required packages to my code. please guide me with this error. Thank you in advance.
library IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
USE IEEE.std_logic_arith.all;
USE IEEE.math_real.all;
library IEEE_proposed;
use IEEE_proposed.fixed_pkg.all;
entity test_zp is
end;
Architecture ARCHofZP of test_zp is
TYPE matrix IS ARRAY ( NATURAL RANGE <>, NATURAL RANGE <> ) OF INTEGER RANGE 0 TO 500;
SIGNAL kernel : matrix ( 1 TO 3 , 1 TO 3 ) := ((1,0,0),(0,1,0),(1,0,1));
SIGNAL image1 : matrix ( 1 To 6 , 1 TO 6 ) := ((25,100,75,49,130,15),(50,80,0,70,100,34),(20,5,10,20,30,0),(45,60,50,12,24,32),(34,37,53,55,21,90),(45,65,55,78,20,16));
FUNCTION batchnorm (outimg : matrix ( 1 To 8 , 1 TO 8 ) ) RETURN matrix IS
VARIABLE sum1 : INTEGER RANGE 0 TO 500;
VARIABLE SD1,SD,mean,ave,sum : UFIXED (10 downto -2):= "00000000";
VARIABLE batchnorm_mat : matrix (outimg'RANGE(1), outimg'RANGE(2));
CONSTANT alpha,beta : UFIXED (1 downto -2):= "0010";
BEGIN
R1 : FOR i IN outimg'RANGE(1) LOOP
C1 : FOR j IN outimg'RANGE(2) LOOP
sum1 := sum1 + outimg(i,j);
END LOOP;
END LOOP;
mean := sum1 / outimg'LENGTH;
ave := to_ufixed(23,10,-2);
R2 : FOR i IN outimg'RANGE(1) LOOP
C2 : FOR j IN outimg'RANGE(2) LOOP
SD1 := ((to_ufixed(outimg(i,j),10,-2)-ave)/to_ufixed(outimg'LENGTH,10,-2)) + SD1;
END LOOP;
END LOOP;
SD := SD1 ** (2);
R3 : FOR i IN batchnorm_mat'RANGE(1) LOOP
C3 : FOR j IN batchnorm_mat'RANGE(2) LOOP
batchnorm_mat(i,j) := ((to_ufixed(outimg(i,j),10,-2) - ave)/(SD)) * alpha + beta ;
END LOOP;
END LOOP;
RETURN batchnorm_mat; -- return batch normalized outimg matrix named batchnorm_mat
END FUNCTION batchnorm;
begin
outimg <= zero_padding( kernel , image1 );
end Architecture ARCHofZP;
Evening all, I have had a similar issue previously with this type of code however I have not been able to figure this one out. I am trying to run my Jacobi code with an initial approximation of the 0 vector, and with tolerance Matrix norm (X^n - x^(n-1)) < 1e^-2
restart;
jacobi:=proc(A::Matrix,b::Vector,x0::Vector,m::integer)
local n,i,j,S,x::Vector,x1::Vector;
x1:=Vector(x0); x := Vector(m);
ee:= LinearAlgebra[VectorNorm](x-x1);
for n from 1 to 50 while ee < 1e-2 do
for i from 1 to m do
S:=0.0;
for j from 1 to m do
if j<>i then S:=S+A[i,j]*x1[j]; end if;
end do;
x[i]:=(-S+b[i])/A[i,i];
end do;
for j from 1 to m do
x1[j]:=x[j];
end do;
print(n,x);
end do;
return x
end proc;
A:=Matrix([[12.4,0.3,-2.2,0.2,3.6],[1.2,7.1,-1.7,-1.6,0.9],[1.3,3.1,10.8,2.2,0.7],[-1.4,0.8,1.1,-7.7,-1.8],[2.8,6.4,0.0,-1.2,-16.6]]);
b:=Vector([-3.5,19.58,-24.56,8.16,-9.28]);
x0:=Vector([0,0,0,0,0]);
jacobi(A,b,x0,5);
#Error, (in jacobi) Vector index out of range
Error, (in LinearAlgebra:-Norm) expects its 1st argument, A, to be of type {Matrix, Vector}, but received x-x1
I found a solution!
restart;
jacobi:=proc(A::Matrix,b::Vector,x0::Vector,m::integer,N::integer,tol::float)
local n,i,j,S,ee,x::Vector,x1::Vector;
x1:=Vector(x0); x := Vector(m); n:=1;
do
for i from 1 to m do
S:=0.0;
for j from 1 to i-1 do
S:=S+A[i,j]*x1[j]
end do;
for j from i+1 to m do
S:=S+A[i,j]*x1[j]
end do;
x[i]:=(-S+b[i])/A[i,i];
end do;
ee:= LinearAlgebra[VectorNorm](x-x1);
if(ee<tol) then
printf("The solution after %d iterations is:",n);
print(x);
break;
end if;
for j from 1 to m do
x1[j]:=x[j];
end do;
n:=n+1;
if (n>N) then error("No convergence after",N,"iterations") end if;
end do;
return x;
end proc;
jacobi := proc(A::Matrix, b::Vector, x0::Vector, m::integer,
N::integer, tol::float)
...
end;
A:=Matrix([[12.4,0.3,-2.2,0.2,3.6],[1.2,7.1,-1.7,-1.6,0.9],[1.3,3.1,10.8,2.2,0.7],[-1.4,0.8,1.1,-7.7,-1.8],[2.8,6.4,0.0,-1.2,-16.6]]);
b:=Vector([-3.5,19.58,-24.56,8.16,-9.28]);
x0:=Vector([0,0,0,0,0]);
jacobi(A,b,x0,5,100,0.01);
The solution after 8 iterations is:
[Yosys 0.8]
A colleague of mine threw some random verilog code to Yosys to see how it reacts.
Here it is:
module top(input clk, input led, output led2, output to_port1,output [24:0] to_port2);
reg ctr = 0;
reg[24:0] counter = 2;
always#(posedge clk) begin
if (ctr == 1) begin
ctr <= 0;
counter <= counter + 1;
end
else
ctr <= 1;
end
assign led2 = ctr;
assign to_port1 = led;
assign to_port2 = counter;
endmodule
and Yosys, with command yosys -o synth.v x.v throws:
module top(clk, led, led2, to_port1, to_port2);
reg [24:0] _0_;
reg _1_;
reg [24:0] _2_;
reg _3_;
wire [31:0] _4_;
wire _5_;
input clk;
reg [24:0] counter;
reg ctr;
input led;
output led2;
output to_port1;
output [24:0] to_port2;
assign _4_ = counter + 32'd1;
assign _5_ = ctr == 32'd1;
always #* begin
_3_ = 1'h0;
end
always #* begin
end
always #({ }) begin
ctr <= _3_;
end
always #* begin
_2_ = 25'h0000002;
end
always #* begin
end
always #({ }) begin
counter <= _2_;
end
always #* begin
_1_ = ctr;
_0_ = counter;
casez (_5_)
1'h1:
begin
_1_ = 1'h0;
_0_ = _4_[24:0];
end
default:
_1_ = 1'h1;
endcase
end
always #(posedge clk) begin
ctr <= _1_;
counter <= _0_;
end
assign led2 = ctr;
assign to_port1 = led;
assign to_port2 = counter;
endmodule
Some constructs end up being complicated. This result code above cannot be compiled by recent verilog compilers when the original can.
Why the always #({ }) begin construct and empty always #* begin?
Is there an option we missed?
Thanks
In general you should always run proc (-p proc) between reading and writing Verilog, due to the nature of Yosys' internal representation of the read-in Verilog
I have a function who should return a letter list of alphabet.
I obtain a table with correct size with nothing inside.
My code :
CREATE OR REPLACE FUNCTION p_get_list(IN nb integer)
RETURNS TABLE(strconcat text) AS
$BODY$DECLARE
i integer;
j integer;
r integer;
strconc text;
BEGIN
j=ASCII('A');
FOR i IN 1..nb LOOP
r=j+i-1;
SELECT chr(r) INTO strconc;
RETURN NEXT;
END LOOP;
end if;
END;$BODY$
Thanks.
you can reuse existing function generate_series for it, eg:
t=# select chr(a) from generate_series(ascii('A'),ascii('A')+25,1) a;
chr
-----
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
S
T
U
V
W
X
Y
Z
(26 rows)
i am trying to find difference of two numbers from set of number available in file. "read.txt" contain numbers as
5
15
25
36
98
654
256
20
354
and i want output as 10 10 11 62 556 398 236 334
but i am getting in my output file "realout.txt" as 0
0
10
11
556
236
236
236
236
236
236
i don't know why every time at starting position 0 is printed and at the end number is repeated 5 times more..please help me to solve this problem my code is here.
library IEEE;
library std;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
use IEEE.MATH_REAL.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_TEXTIO.ALL;
use std.textio.all; --include package textio.vhd
entity testvhdl is
end testvhdl;
architecture Behavioral of testvhdl is
constant MAX : integer := 256*256-1;
SIGNAL rstb : std_logic := '0';
SIGNAL clk : std_logic := '0';
SIGNAL a : std_logic_vector(7 downto 0) := (others=>'0');
--Outputs
SIGNAL sum : std_logic_vector(7 downto 0);
--period of clock,bit for indicating end of file.
signal endoffile : bit := '0';
signal d1,d2,intt,n: integer:=0;
signal aa,ab,ac: integer:=0;
signal linenumber : integer:=1;
--signal dbus: std_logic_vector(7 downto 0) := x"00";
--------------------------------------------------------------------------------------------
function CONV_STDLV8bit_2INT(ARG: std_logic_vector (7 downto 0))
return integer is
variable int: integer:=0;
variable tmp: std_logic_vector(7 downto 0);
begin
int :=0;
tmp := ARG;
for i in 0 to 7 loop
if (tmp(i) ='1') then
int := int+(2**i);
else
int := int+0;
end if;
end loop;
return int;
end CONV_STDLV8bit_2INT;
--------------------------------------------------------------------------------------------
function CONV_INT2STDLV(ARG: INTEGER; SIZE: INTEGER)
return STD_LOGIC_VECTOR is
variable result: STD_LOGIC_VECTOR (SIZE-1 downto 0):=x"00";
variable temp: integer:= 0;
begin
temp := ARG;
for i in 0 to SIZE-1 loop
if ((temp mod 2) = 1) then
result(i) := '1';
else
result(i) := '0';
end if;
if temp > 0 then
temp := temp / 2;
elsif (temp > integer'low) then
temp := (temp - 1) / 2; -- simulate ASR
else
temp := temp / 2; -- simulate ASR
end if;
end loop;
return result;
end CONV_INT2STDLV;
--------------------------------------------------------------------------------------------
constant PERIOD : time := 20 ns;
constant DUTY_CYCLE : real := 0.5;
constant OFFSET : time := 30 ns;
begin
-- Instantiate the Unit Under Test (UUT)
--uut: imadder PORT MAP(
-- rstb => rstb,
-- clk => clk,
-- a => a,
-- b => b,
-- sum => sum
-- );
CLOCK: PROCESS -- clock process for clk
BEGIN
WAIT for OFFSET;
CLOCK_LOOP : LOOP
clk <= '0';
WAIT FOR (PERIOD - (PERIOD * DUTY_CYCLE));
clk <= '1';
WAIT FOR (PERIOD * DUTY_CYCLE);
END LOOP CLOCK_LOOP;
END PROCESS;
tb: PROCESS
BEGIN
rstb <='0';
wait for 60ns;
rstb <='1';
wait for 1312us; -- will wait forever
END PROCESS;
reading : process
file infile : text is in "real.txt"; --declare input file 1987
file outfile : text is out "realout.txt"; --declare output file 1987
--file infile2 : text is in "img2.txt"; --declare input file 1987
variable inline,inline2 : line; --line number declaration
variable dataread1 : integer;
variable dataread2 : integer;
variable buff_out : line; --line number declaration
-- variable aa,ab,ac: integer:=0;
begin
wait until clk = '0' and clk'event;
if(n < 10) then
if (not (endfile(infile))) then --checking the "END OF FILE" is not reached.
readline(infile, inline);
readline(infile, inline2);
read(inline, dataread1);
read(inline2, dataread2);
d1 <= dataread1;
d2 <= dataread2;
-- if n mod 5 = 0 then
aa <= abs(d1 - d2);
-- a <= CONV_INT2STDLV(aa,8);
--
-- n <= n+1;
-- elsif (d1 > aa) then
-- ab <= d1 - aa;
-- ac <= ac+ab;
-- aa <= d1;
--
-- else
-- ab <= aa - d1;
-- ac <= ac+ab;
-- aa <= d1;
--
-- end if;
-- d1 <= ac;
--readline(infile2, inline2);
--read(inline2, dataread1);
--d2 <=integer(dataread1);
--b <= CONV_INT2STDLV(d2,8);
else
a<=x"00";
--b<=x"00";
end if;
else
endoffile <='1'; --set signal to tell end of file read file is reached.
end if;
-- end process reading;
--write process #negative edge
--writing : process
-- begin
-- wait until clk = '0' and clk'event;
if(endoffile='0') then --if the file end is not reached.
--intt <= CONV_STDLV8bit_2INT(aa);
if(linenumber > 0) then
n <= n+1;
--if(linenumber>11) then
write(buff_out, aa);
writeline(outfile, buff_out);-- write line to output_image text file.
--end if;
end if;
linenumber <= linenumber + 1;
else
null;
end if;
end process reading;
end Behavioral;
--WRITE (buf, string'("hello"));
--WRITELINE(fileptr,buf);
--WRITE (buf, bit_vector'(" 010111 "));
--WRITELINE(fileptr,buf);
--http://myfpgablog.blogspot.in/2011/12/memory-initialization-methods.html
-- constant MEM_DEPTH : integer := 2**ADDR_WIDTH;
-- type mem_type is array (0 to MEM_DEPTH-1) of signed(DATA_WIDTH-1 downto 0);
-- impure function init_mem(mif_file_name : in string) return mem_type is
-- file mif_file : text open read_mode is mif_file_name;
-- variable mif_line : line;
-- variable temp_bv : bit_vector(DATA_WIDTH-1 downto 0);
-- variable temp_mem : mem_type;
-- begin
-- for i in mem_type'range loop
-- readline(mif_file, mif_line);
-- read(mif_line, temp_bv);
-- temp_mem(i) := signed(to_stdlogicvector(temp_bv));
-- end loop;
-- return temp_mem;
-- end function;
-- constant mem : mem_type := init_mem("mem_init_vhd.mif");
...i don't know why every time at starting position 0 is printed and at the end number is repeated 5 times more..please help me to solve this problem my code is here.
Besides the wild context clauses and all the extraneous noise there are two things observably wrong here. First you proposed input data set for real.txt has an odd number of lines (elements - integers). Second you are misapplying the BIT signal endofile:
reading :
process
file infile : text is in "real.txt";
file outfile : text is out "realout.txt";
variable inline,inline2 : line;
variable dataread1 : integer;
variable dataread2 : integer;
variable buff_out : line;
begin
wait until clk = '0' and clk'event;
if(n < 10) then
if (not (endfile(infile))) then
readline(infile, inline);
readline(infile, inline2);
read(inline, dataread1);
read(inline2, dataread2);
d1 <= dataread1;
d2 <= dataread2;
aa <= abs(d1 - d2);
else
a<=x"00";
end if;
else
endoffile <='1';
end if;
if(endoffile='0') then
if(linenumber > 0) then
n <= n+1;
write(buff_out, aa);
writeline(outfile, buff_out);
end if;
linenumber <= linenumber + 1;
else
null;
end if;
end process reading;
This is what your design with less than 20 integers on separate lines looks like:
As you can see from the waveform that results in the last value being repeated (the falling edge of the following clocks).
I added the 720 so it wouldn't get an integer read fail assertion.
The first two zeros are from not holding off output when rstb is true and a pipeline delay loading d0, d1 on a falling clock edge and then assigning aa on the next clock edge. There isn't a pipeline signal to qualify aa as valid for output.
endofile will never get written to a '1' where that assignment is unless your data set is big enough. n is counting input pairs of integers (pairs of lines):
So endofile should be fixed (on two counts, it's not set when an end of file condition is actually encountered, and the second readline is assumed to have been successful).
There's a third thing wrong, with enough data from real.txt you're missing the last absolute difference value in realout.txt, which says that pipeline signal specifying aa is valid should have a hold over as well as a hold off.
It might be easier to fix this by troubleshooting waveforms.
For the portion of your code not commented out the context clause should look like this:
library IEEE;
use ieee.std_logic_1164.all;
use std.textio.all;