Why the procedure doesn't see the variable? - variables

Question

I'm using Xilinx ISE to create a VHDL project.
I'm trying to add values to an integer variable.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity vending2_mod is
Port ( button1 : in STD_LOGIC;
button2 : in STD_LOGIC;
button3 : in STD_LOGIC;
button4 : in STD_LOGIC;
coin : in integer;
disp : out string(1 to 16);
prodOut : out integer);
shared variable credits : integer := 0;
procedure addCredits ( c : in integer ) is
begin
credits := credits + c; -- Signal is not defined : 'credits'.
end addCredits;
-- additional code
end vending2_mod;
architecture Behavioral of vending2_mod is
begin
acceptCredit: process (coin)
begin
addCredits(coin);
end process;
end Behavioral;
Yet when I try to Synthesize (XST) the project, I'm getting an error to the line I've written it as a comment. The credits is not a signal, it is a variable; what gives the error?
Saving gives no errors, since the syntax seems to be correct.

Answer 1

Entity-statements must be -passive statements, that is, they must not
assign values to any signals.
Don't use shared variables.
In simulation, variables update immediately upon assignment, as opposed to signals, which are updated only at the end of a simulation cycle. In combinational code, signals immediately take the value of their assignment. In sequential code, signals are used to create flip-flops, which inherently do not immediately take the value of their assignment.
it is better to use signal+clock instead.
Try this:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity vending2_mod is
port(
Clock: in std_logic;
Reset: in std_logic;
coin : in integer;
prod_out : out integer
);
end vending2_mod;
architecture Behavioral of vending2_mod is
signal credits : integer := 0;
begin
process(Clock,Reset)
begin
if Reset='1' then
credits <= 0;
elsif(rising_edge(Clock)) then
credits <= credits + coin;
end if;
end process;
prod_out <= credits;
end Behavioral;
See elaborated design:
Don't try this (synthesis OK, note: You need clock):
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity vending2_mod is
Port (
coin : in integer;
prod_out : out integer);
end vending2_mod;
architecture Behavioral of vending2_mod is
signal credits : integer := 0;
begin
credits <= credits + coin;
prod_out <= credits;
end Behavioral;
See elaborated design: