Priority 8-to-3 encoder in Verilog (case, casex) - authentication

Question

I'm trying to describe a SN54LS348 element (8-line to 3-line priority encoder).
The truth table is:
INPUTS OUTPUTS
E | 0 1 2 3 4 5 6 7 ** A2 A1 A0 | GS EO
///////////////////////////////////////
H | X X X X X X X X ** Z Z Z | H H
L | H H H H H H H H ** Z Z Z | H L
L | X X X X X X X L ** L L L | L H
L | X X X X X X L H ** L L H | L H
L | X X X X X L H H ** L H L | L H
L | X X X X L H H H ** L H H | L H
L | X X X L H H H H ** H L L | L H
L | X X L H H H H H ** H L H | L H
L | X L H H H H H H ** H H L | L H
L | L H H H H H H H ** H H H | L H
Here's my implementation:
module L348 (E, D0, D1, D2, D3, D4, D5, D6, D7, A0, A1, A2, GS, EO);
input E, D0, D1, D2, D3, D4, D5, D6, D7;
output A0, A1, A2, GS, EO;
assign D = {D0, D1, D2, D3, D4, D5, D6, D7};
parameter HIGH_IMPEDANCE = 3'bz;
reg [7:0] MASK_1 = 8'b0000_0001;
reg [7:0] MASK_2 = 8'b0000_0011;
reg [7:0] MASK_3 = 8'b0000_0111;
reg [7:0] MASK_4 = 8'b0000_1111;
reg [7:0] MASK_5 = 8'b0001_1111;
reg [7:0] MASK_6 = 8'b0011_1111;
reg [7:0] MASK_7 = 8'b0111_1111;
reg [7:0] MASK_8 = 8'b1111_1111;
reg [2:0] A;
reg [1:0] GS_EO;
reg [7:0] temp;
reg [7:0] mem [7:0];
initial
begin
mem[0] = MASK_1;
mem[1] = MASK_2;
mem[2] = MASK_3;
mem[3] = MASK_4;
mem[4] = MASK_5;
mem[5] = MASK_6;
mem[6] = MASK_7;
mem[7] = MASK_8;
temp = 8'bxxxx_xxxx;
end
assign {A2, A1, A0} = A;
assign {GS, EO} = GS_EO;
integer i;
always #(*)
begin
for (i = 7; i > 0; i = i - 1)
if (mem[i] & D == mem[i])
begin
temp = mem[i];
i = -1;
end
if (E)
begin
A = HIGH_IMPEDANCE;
GS_EO = 2'b11;
end
else
begin
if (temp == 8'b1111_1111)
begin
A = HIGH_IMPEDANCE;
GS_EO = 2'b10;
end
else
begin
GS_EO = 2'b01;
case (temp)
8'b0000_0001: A = 3'b001;
8'b0000_0011: A = 3'b010;
8'b0000_0111: A = 3'b011;
8'b0000_1111: A = 3'b100;
8'b0001_1111: A = 3'b101;
8'b0011_1111: A = 3'b110;
8'b0111_1111: A = 3'b111;
endcase
end
end
end
endmodule
It fails to achieve the switching of signals A2-A0 which are always in a X-state (except when E = H). I've tried many solutions, but it feels like simulator can't manage 'case' block ( I tried also 'casex' block). There is a bug somewhere, but I can't figure it out. Does anyone have ideas?

Answer 1

You've got quite a few things going on here but your most immediate problem is probably.
assign D = {D0, D1, D2, D3, D4, D5, D6, D7};
This implicitly defined wire is only going to be 1 bit wide and so the high 7b are going to be dropped. Isn't Verilog fun?
There are other logical problems but the easiest way of doing a priority encoder with a case statement is as follows:
casez (in)
4'b???1 : out = 0;
4'b??10 : out = 1;
4'b?100 : out = 2;
4'b1000 : out = 3;
default : out = 0; //no match
endcase
The casez allow you to put in ? for don't care conditions similar to your truth table. The first matching entry is taken which give you the priority behavior.
Adapt as needed for your case for width, direction of priority, width of IO, etc...
Finally as a stylistic concern your early loop termination should use break rather than directly modifying the loop variable.