My problem seems really simple but somehow I can't get it to work.
I am trying to create a module in verilog which outputs a 3bit signal. I've tried so many different methods so far but none of them seem to work.
I am using Veriwell to compile my code and since I am doing this for university I am oblieged to use it so please don't recommend me different compilers.
Here are some methods I've tried but none of them worked
(I always get a 'Port sizes don't match in port #2' warning)
module testmod (in, out);
input [2:0] in;
output [2:0] out;
wire [2:0] out;
assign out = in; //trying just to connect in to out
endmodule
module testmod (in, out);
input [2:0] in;
output [2:0] out;
wire [2:0] out;
assign out = 3'b1; //trying to assign a random value to out
endmodule
module testmod (in, out);
input [2:0] in;
output [2:0] out;
reg [2:0] test;
always #(in)
test = in; //saving in in a register (which i believe is unnecessary but I've tried it nonetheless)
wire [2:0] out;
assign out = test; //trying just to connect in to out
endmodule
I instanciate the module like this:
testmod mod (.in(3'b1), .out(out));
Declaring out as a 3-bit signal in my testbench did the job. Since I've only worked with 1-bit output signals which apparently don't need to be declared at all in the testbench this didn't even come to my mind.
Related
I have made a low pass filter in verilog. I have also made a testbench for it. The main verilog code seems to be compiled without any error. However, when I try to compile the testbench I encounter an error which I could not resolve it. I appreciate if anyone can help me about it.
here is the code:
module Testbench_S;
//Inputs
reg clk;
reg clkR;
reg clk_enable;
reg en;
reg reset;
reg [7:0] filter_in;
//reg clk, reset, en;
wire [7:0] sine, cos;
reg [7:0] sine_r, cos_r;
assign sine = sine_r +(cos_r[7],cos_r[7], cos_r[7], cos_r[7:3]);
assign cos = cos_r -(sine[7],sine[7],sine[7],sine[7:3]);
//some other codes
endmodule
the error is as follow
Error: (vlog-13069) C:/CommonFiles/FPGA/hdlsrc/Testbench_S.v(14): near ",": syntax error, unexpected ','.
Error: (vlog-13069) C:/CommonFiles/FPGA/hdlsrc/Testbench_S.v(15): near ",": syntax error, unexpected ','.
You use (cos_r[7],cos_r[7], cos_r[7], cos_r[7:3]) where you probably wanted to concatenate the bits.
The operator for concatenation is {...} (curly brackets no round brackets)
I've been testing yosys for some use cases.
Version: Yosys 0.7+200 (git sha1 155a80d, gcc-6.3 6.3.0 -fPIC -Os)
I wrote a simple block which converts gray code to binary:
module gray2bin (gray, bin);
parameter WDT = 3;
input [WDT-1:0] gray;
output [WDT-1:0] bin;
assign bin = {gray[WDT-1], bin[WDT-1:1]^gray[WDT-2:0]};
endmodule
This is an acceptable and valid code in verilog, and there is no loop in it.
It passes compilation and synthesis without any warnings in other tools.
But, when I run in yosys the next commands:
read_verilog gray2bin.v
scc
I get that a logic loop was found:
Found an SCC: $xor$gray2bin.v:11$1
Found 1 SCCs in module gray2bin.
Found 1 SCCs.
The next code, which is equivalent, pass the check:
module gray2bin2 (
gray,
bin
);
parameter WDT = 3;
input [WDT-1:0] gray;
output [WDT-1:0] bin;
assign bin[WDT-1] = gray[WDT-1];
genvar i;
generate
for (i = WDT-2; i>=0; i=i-1) begin : gen_serial_xor
assign bin[i] = bin[i+1]^gray[i];
end
endgenerate
endmodule
Am I missing a flag or synthesis option of some kind?
Using word-wide operators this circuit clearly has a loop (generated with yosys -p 'prep; show' gray2bin.v):
You have to synthesize the circuit to a gate-level representation to get a loop-free version (generated with yosys -p 'synth; splitnets -ports; show' gray2bin.v, the call to splitnets is just there for better visualization):
The answer given by CliffordVienna indeed gives a solution, but I also want to clarify that that it's not suitable to all purposes.
My analysis was done for the purpose of formal verification. Since I replaced the prep to synth to solve the falsely identified logic loops, my formal code got optimized. Wires which I've created that were driven only by the assume property pragma, were removed - this made many assertions redundant.
It's not correct to reduce any logic for the purpose of behavioral verification.
Therefore, if the purpose is to prepare a verification database, I suggest not to use the synth command, but to use a subset of commands the synth command executes.
You can find those commands under:
http://www.clifford.at/yosys/cmd_synth.html
In general, I've used all the commands specified in the above link that do not optimize logic:
hierarchy -check
proc
check
wreduce
alumacc
fsm
memory -nomap
memory_map
techmap
abc -fast
hierarchy -check
stat
check
And everything works as expected.
I am trying to see if Yosys fits my requirements or no.
What i want to do is to find an operation in Verilog code (e.g. temp = 16*val1 + 8*val2 ) and replace this with another op like ( temp = val1 << 4 + val2 << 3 ).
Which parts i need to learn & use from Yosys? if anyone knows the set of command to use, can he/she please let me know to boost my learning curve ?
Thanks.
For example consider the following verilog input (test.v):
module test(input [7:0] val1, val2, output [7:0] temp);
assign temp = 16*val1 + 8*val2;
endmodule
The command yosys -p 'prep; opt -full; show' test.v will produce the following circuit diagram:
And the output written to the console contains this:
3.1. Executing OPT_EXPR pass (perform const folding).
Replacing multiply-by-16 cell `$mul$test.v:2$1' in module `\test' with shift-by-4.
Replacing multiply-by-8 cell `$mul$test.v:2$2' in module `\test' with shift-by-3.
Replacing $shl cell `$mul$test.v:2$1' (B=3'100, SHR=-4) in module `test' with fixed wiring: { \val1 [3:0] 4'0000 }
Replacing $shl cell `$mul$test.v:2$2' (B=2'11, SHR=-3) in module `test' with fixed wiring: { \val2 [4:0] 3'000 }
The two lines reading Replacing multiply-by-* cell are the transformation you mentioned. The two lines after that replace the constant shift operations with wiring, using {val1[3:0], 4'b0000} and {val2[4:0], 3'b000} as inputs for the adder.
This is done in the opt_expr pass. See passes/opt/opt_expr.cc for its source code to see how it's done.
I'm trying to do some image processing with FPGA and my supporter want us to show some simulation result with Modelsim.
So, basically we try to read image file in testbench and write it to another file but it stop read file at half of the file. Here is my source code
module fileio1;
integer in,out,r;
reg [31:0]temp;
reg clk;
initial
begin
r=0;
temp =0;
clk = 0;
in = $fopen("test120.bmp","r");
out = $fopen("result.bmp","w");
end
always #1 clk = ~clk;
always #(negedge clk)
begin
r = $fscanf(in,"%c",temp);
end
always #(posedge clk)
begin
if(~r) $fwrite(out,"%c",temp);
end
endmodule
This is that source code and our input file is 120x180 size bitmapfile (64kb)
but output file is 38kb. Almost half of file. I try it with 480x720 size bitmapfile(1013kb), it's ouput file is almost half of the origin file too.
With very small size file input, we can get the right outputfile.
Why is this happen? Is there some better function to input/output file?
You should not use $fscanf in that situation. $fscanf skips over white-space, including blank lines (just like fscanf() function in C).
You should rather use $fread function:
always #(negedge clk)
begin
r = $fread(temp,in);
end
I am writing a simple flipflop module in verilog and I am trying to write a top level module in instantiate my flipflop module and simulate it in ModelSim.
Here is my code below,
module flipflop(clck,D,Q);
input clck,D;
output Q;
wire R,S,S_g,R_g,Qa,Qb;
assign R = ~D;
assign S = D;
nand(S_g,S,clck);
nand(R_g,R,clck);
nand(Qa,S_g,Qb);
nand(Qb,R_g,Qa);
assign Q = Qa;
endmodule
module TopLevel();
reg clck;
reg Q;
wire D;
flipflop p1(clck,D,Q);
always begin
#5 clck <=1;
#5 clck <=0;
end
endmodule
When I compile this code it runs fine, but when I try to simulate it, I get the following error:
# ** Error: (vsim-3053) C:/altera/13.1/FlipFlopsProjects/flipflop.v(30): Illegal output or inout port connection for "port 'Q'".
Any ideas or thoughts?
Error was in the declaration of inputs for the top level module...they needed to be wires, not regs
In top module, Q needed to be regs and D needed to be wires.