I am writing a simple flipflop module in verilog and I am trying to write a top level module in instantiate my flipflop module and simulate it in ModelSim.
Here is my code below,
module flipflop(clck,D,Q);
input clck,D;
output Q;
wire R,S,S_g,R_g,Qa,Qb;
assign R = ~D;
assign S = D;
nand(S_g,S,clck);
nand(R_g,R,clck);
nand(Qa,S_g,Qb);
nand(Qb,R_g,Qa);
assign Q = Qa;
endmodule
module TopLevel();
reg clck;
reg Q;
wire D;
flipflop p1(clck,D,Q);
always begin
#5 clck <=1;
#5 clck <=0;
end
endmodule
When I compile this code it runs fine, but when I try to simulate it, I get the following error:
# ** Error: (vsim-3053) C:/altera/13.1/FlipFlopsProjects/flipflop.v(30): Illegal output or inout port connection for "port 'Q'".
Any ideas or thoughts?
Error was in the declaration of inputs for the top level module...they needed to be wires, not regs
In top module, Q needed to be regs and D needed to be wires.
Related
This question already has answers here:
register is being called a net in my testbench -- won't compile
(1 answer)
Problem with error (vlog-2110) Illegal reference to net
(1 answer)
Closed 9 months ago.
I am writing a code for finding a path by north last routing in NOC. I have not declared any of the inputs as inout but still the error given below is shown. This error is popping up for literally all of the codes I write. Where is the problem?
I am providing my code and testbench here.
code:
timescale 1ns / 1ps
module mesh (
input [15:0] a,
input [1:0] c_x,
input [1:0] c_y ,
output [3:0] port
);
reg d_x=0,d_y=0,s_x=0,s_y=0;
always # (a or c_x or c_y)//when cx or cy changes, this loop happens
begin
d_x=a[1:0];// x coordinate of destination address
d_y=a[3:2];//y coordinate of destination address
s_x=a[5:4];// x coordinate of source addres
s_y=a[7:6];// y coordinate of source addres
comp u1(
.a(a),
.c_x(c_x),
.c_y(c_y),
.port(port)
);
end
endmodule
testbench:
`timescale 1ns / 1ps
module north_tb(
reg [15:0] a,
reg [1:0] c_x,
reg [1:0] c_y ,
wire [3:0] port
);
mesh u1(
.a(a),
.c_x(c_x),
.c_y(c_y),
.port(port)
);
initial
begin
a[15:0] = 16'b100110101001010;//
c_x=2'b01;
c_y =2'b00;
#5
c_x=2'b01;
c_y =2'b01;
#5
c_x=2'b01;
c_y =2'b10;
#5
c_x=2'b10;
c_y =2'b10;
#5
$finish;
end
endmodule
following is the error message:
ERROR: [VRFC 10-1145] non-net port d_x cannot be of mode inout [D:/Vivado/northlast/northlast.srcs/sim_1/new/comp_tb.v:4]
ERROR: [VRFC 10-1145] non-net port d_y cannot be of mode inout [D:/Vivado/northlast/northlast.srcs/sim_1/new/comp_tb.v:5]
ERROR: [VRFC 10-1145] non-net port c_x cannot be of mode inout [D:/Vivado/northlast/northlast.srcs/sim_1/new/comp_tb.v:6]
ERROR: [VRFC 10-1145] non-net port c_y cannot be of mode inout [D:/Vivado/northlast/northlast.srcs/sim_1/new/comp_tb.v:7]
ERROR: [VRFC 10-1040] module comp_tb ignored due to previous errors [D:/Vivado/northlast/northlast.srcs/sim_1/new/comp_tb.v:3]
Testbench's generally do not have ports.
The simulator does not like the way the posted testbench is using ports for access to design under test (DUT).
The way for the testbench to access the DUT is by using signals declared locally in the testbench.
Like this:
// testbench module does not have ports
module north_tb();
// use local signals to access the DUT
reg [15:0] a ;
reg [1:0] c_x ;
reg [1:0] c_y ;
wire [3:0] port;
mesh u1(
.a(a),
.c_x(c_x),
.c_y(c_y),
.port(port)
);
initial
begin
a[15:0] = 16'b100110101001010;//
c_x=2'b01;
c_y =2'b00;
#5
c_x=2'b01;
c_y =2'b01;
#5
c_x=2'b01;
c_y =2'b10;
#5
c_x=2'b10;
c_y =2'b10;
#5
$finish;
end
endmodule
The post has a problem in the mesh module. It instantiates a module called comp which is not provided in the post. I don't think this is the problem that triggered post though.
I think the problem is trying to have ports on the testbench module, and expecting them to function as local signals.
Could in be that all the code you write have ports on the testbenches?
In the mesh module this statement is bad for a couple of reasons.
always # (a or c_x or c_y)//when cx or cy changes, this loop happens
A recommendation is to replace it with
always # (*)
I have made a low pass filter in verilog. I have also made a testbench for it. The main verilog code seems to be compiled without any error. However, when I try to compile the testbench I encounter an error which I could not resolve it. I appreciate if anyone can help me about it.
here is the code:
module Testbench_S;
//Inputs
reg clk;
reg clkR;
reg clk_enable;
reg en;
reg reset;
reg [7:0] filter_in;
//reg clk, reset, en;
wire [7:0] sine, cos;
reg [7:0] sine_r, cos_r;
assign sine = sine_r +(cos_r[7],cos_r[7], cos_r[7], cos_r[7:3]);
assign cos = cos_r -(sine[7],sine[7],sine[7],sine[7:3]);
//some other codes
endmodule
the error is as follow
Error: (vlog-13069) C:/CommonFiles/FPGA/hdlsrc/Testbench_S.v(14): near ",": syntax error, unexpected ','.
Error: (vlog-13069) C:/CommonFiles/FPGA/hdlsrc/Testbench_S.v(15): near ",": syntax error, unexpected ','.
You use (cos_r[7],cos_r[7], cos_r[7], cos_r[7:3]) where you probably wanted to concatenate the bits.
The operator for concatenation is {...} (curly brackets no round brackets)
I have a couple of errors in my verilog code that pop up when I compile. I believe they are all related. But I can't figure out what the error is. Any help will be greatly appreciated.
The errors are: Two for the input
vlog_a: Error 31004 Syntax error near `input' found
blog_a: Error 31004 Syntax error near 'output' found
module threeBitComparator;
input A2,A1,A0;
input B2,B1,B0;
output E,GE; //E-Equal, GE-Greater than or Equal to
wire X1,X2,X3; //xnor gate
wire Y1,Y2,Y3,Y4,Y5,Y6; // and & or gates
xnor
G1a(X1,A2,B2),
G1b(X2,A1,B1),
G1c(X3,A0,B0);
and
G2a(Y1,A2,~B2),
G2b(Y2,A1,~B1),
G2c(Y3,A0,~B0),
G2d(Y4,X1,Y2),
G2e(Y5,X1,X2,Y3),
G2f(E,X1,X2,X3);
or
G3a(Y6,Y1,Y4,Y5),
G3b(GE,Y6,E);
endmodule
You declared your inputs and outputs but you haven't declared a port list. Your module header needs to look like below code to be IEEE 1364-1995 complaint
module threeBitComparator(A2,A1,A0,B2,B1,B0,E,GE); // <-- port list
input A2,A1,A0;
input B2,B1,B0;
output E,GE; //E-Equal, GE-Greater than or Equal to
Or you can use the ANSI style header introduce in IEEE Std 1364-2001. This style works on any modern Verilog simulator.
module threeBitComparator(
input A2,A1,A0,
input B2,B1,B0,
output E,GE ); //E-Equal, GE-Greater than or Equal to
I think you forgot to declare your input and output in the module port lists. Adding A2, A1..., etc to the port list will solve the compilation errors.
You can check the updated code here.
I am using Xilinx Vivado 2015.2 64 bit.
While running the following simulation I am getting the following error:
FATAL_ERROR: Vivado simulator Kernel has discovered an exceptional condition from which it cannot recover. Process will terminate.
Now the module:
module q();
wire a,b;
endmodule
Test bench for the module:
module tb_q();
reg a,b;
int gan [4] [$];
initial
begin
gan[2].push_back(67);
$monitor("gan= %p",gan);
end
endmodule
Any help will be deeply appreciated.
Thanks.
I believe simulator support of SystemVerilog is limited to a synthesizable subset. http://www.xilinx.com/support/answers/59002.html
I am trying to see if Yosys fits my requirements or no.
What i want to do is to find an operation in Verilog code (e.g. temp = 16*val1 + 8*val2 ) and replace this with another op like ( temp = val1 << 4 + val2 << 3 ).
Which parts i need to learn & use from Yosys? if anyone knows the set of command to use, can he/she please let me know to boost my learning curve ?
Thanks.
For example consider the following verilog input (test.v):
module test(input [7:0] val1, val2, output [7:0] temp);
assign temp = 16*val1 + 8*val2;
endmodule
The command yosys -p 'prep; opt -full; show' test.v will produce the following circuit diagram:
And the output written to the console contains this:
3.1. Executing OPT_EXPR pass (perform const folding).
Replacing multiply-by-16 cell `$mul$test.v:2$1' in module `\test' with shift-by-4.
Replacing multiply-by-8 cell `$mul$test.v:2$2' in module `\test' with shift-by-3.
Replacing $shl cell `$mul$test.v:2$1' (B=3'100, SHR=-4) in module `test' with fixed wiring: { \val1 [3:0] 4'0000 }
Replacing $shl cell `$mul$test.v:2$2' (B=2'11, SHR=-3) in module `test' with fixed wiring: { \val2 [4:0] 3'000 }
The two lines reading Replacing multiply-by-* cell are the transformation you mentioned. The two lines after that replace the constant shift operations with wiring, using {val1[3:0], 4'b0000} and {val2[4:0], 3'b000} as inputs for the adder.
This is done in the opt_expr pass. See passes/opt/opt_expr.cc for its source code to see how it's done.