How to use an entity inside an architecture in VHDL - entity

Question

My purpose is to impement a Keyboard entity which uses Button entites.
So I wrote the following VHDL code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Keyboard is
port ( ck, stop : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (11 downto 0);
data_out : out STD_LOGIC_VECTOR (3 downto 0));
end Keyboard;
entity Button is
port ( clk : in STD_LOGIC ;
signal_in : in STD_LOGIC;
output : out STD_LOGIC);
end Button;
architecture test of Keyboard is
signal NUM : STD_LOGIC_VECTOR (11 downto 0) := (others=>'0');
component Button is
port ( clk : in STD_LOGIC ;
signal_in : in STD_LOGIC;
output : out STD_LOGIC);
end component;
begin
num_0 : entity Button port map(ck,data_in(0),NUM(0));
num_1 : entity Button port map(ck=>clk,data_in(1)=>signal_in,NUM(1)=>output);
num_2 : entity Button port map(ck=>clk,data_in(2)=>signal_in,NUM(2)=>output);
num_3 : entity Button port map(ck=>clk,data_in(3)=>signal_in,NUM(3)=>output);
num_4 : entity Button port map(ck=>clk,data_in(4)=>signal_in,NUM(4)=>output);
num_5 : entity Button port map(ck=>clk,data_in(5)=>signal_in,NUM(5)=>output);
num_6 : entity Button port map(ck=>clk,data_in(6)=>signal_in,NUM(6)=>output);
num_7 : entity Button port map(ck=>clk,data_in(7)=>signal_in,NUM(7)=>output);
num_8 : entity Button port map(ck=>clk,data_in(8)=>signal_in,NUM(8)=>output);
num_9 : entity Button port map(ck=>clk,data_in(9)=>signal_in,NUM(9)=>output);
num_on : entity Button port map(ck=>clk,data_in(10)=>signal_in,NUM(10)=>output);
num_off : entity Button port map(ck=>clk,data_in(11)=>signal_in,NUM(11)=>output);
output <= "0000" when NUM = "000000000001" else --0
"0001" when NUM = "000000000010" else --1
"0010" when NUM = "000000000100" else --2
"0011" when NUM = "000000001000" else --3
"0100" when NUM = "000000010000" else --4
"0101" when NUM = "000000100000" else --5
"0110" when NUM = "000001000000" else --6
"0111" when NUM = "000010000000" else --7
"1000" when NUM = "000100000000" else --8
"1001" when NUM = "001000000000" else --9
"1010" when NUM = "010000000000" else --ON
"1100" when NUM = "100000000000" else --OFF
"1111";
end test;
architecture EdgeDetector of Button is
signal signal_d:STD_LOGIC;
begin
process(clk)
begin
if clk= '1' and clk'event then
signal_d<=signal_in;
end if;
end process;
output<= (not signal_d) and signal_in;
end EdgeDetector;
By starting the compilation on QuartusII I face the following error:
Error (10482): VHDL error at PitAlarm.vhd(11): object "STD_LOGIC" is
used but not declared
But I can't understand what it means with "not declared" ???

Answer 1

Using "direct entity instantiation" you are explicitly binding an entity out of a specific library instead of using "configurations" or some default strategy to find a matching one. So, num_0 : entity Work.Button port map(...); - note the explicit library name (here, Work).
The specific error you find
std_logic not declared
comes from the visibility rules for library clauses.
Button's own entity/arch will normally be in a separate file, separately compiled before compiling the top level.
It would then have its own library/use clauses for the library where std_logic is declared.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
With more than one entity in the same file, this clause only applies to the following entity declaration (and makes it visible o the corresponding architectures).
So you need to repeat these two lines before each entity declaration in the file.