Iteration limit reached - simple counter in VHDL FSM - iteration

Question

I'm having "Iteration limit reached" error in a simple FSM.
This is a part of of a bigger FSM I have to do for a class assignment, and I tracked the problem to this specific part.
The FSM will be controlling a counter, the state IDLE waits for inputs, ZERO sets the counter to zero, and the INCREMENT state increments the counter by one.
When simulating, the error occurs at the first time the input "inc" is high and the clock rises.
If I change the statement "temp := temp + 1;" for "temp := anything" the error stops. I really don't know what can be wrong, as for what I have found this error occurs when changing signals in the process sensitivity list inside the process itself.
I'm using Quartus II for the simulation.
Sorry for english mistakes.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.all;
entity fsm is
port
(
clock: in std_logic;
reset: in std_logic;
inc: in std_logic;
count: out std_logic_vector (13 downto 0);
cur_state: out std_logic_vector (1 downto 0)
);
end fsm;
architecture behaviour of fsm is
type state_type is (IDLE, INCREMENT, ZERO);
signal PS, NS: state_type;
begin
sync_proc: process (clock, reset)
begin
if (reset = '1') then
PS <= ZERO;
elsif (rising_edge(clock)) then
PS <= NS;
end if;
end process sync_proc;
comb_proc: process (PS, inc)
variable temp: unsigned (13 downto 0);
begin
case PS is
when IDLE =>
if (inc = '1') then
NS <= INCREMENT;
else
NS <= IDLE;
end if;
when INCREMENT =>
temp := temp + 1;
NS <= IDLE;
when ZERO =>
temp := "00000000000000";
NS <= IDLE;
when others =>
NS <= IDLE;
end case;
count <= std_logic_vector(temp);
end process comb_proc;
with PS select
cur_state <= "00" when IDLE,
"01" when INCREMENT,
"10" when ZERO,
"11" when others;
end behaviour;

Answer 1

You have a very serious CONCEPTUAL mistake in your case statement. Because it produces a combinational circuit (the combinational part of your FSM), it does not have memory, so it can't implement the equation "temp := temp + 1" (because, having no memory, it doesn't know what the value of temp is).
You can see more about this in chapter 11 of "Finite State Machines in Hardware...", by V.Pedroni, published by MIT.