So I am designing a serial squarer. My program takes a basic binary counter, and uses each count of the counter to calculate squares in series. When I try to synthesize my code, depending on how I arrange my code, either synthesis runs almost infinitely, or the synthesis run just crashes entirely. So I figured that I cannot update my signal r_final => r_final + r_min1 because I remember that not being a thing in vhdl. So I have decided that I need to set r_final to a variable instead of a signal. I'm not sure how I should declare r_final as a variable. Can anyone provide some insight on how I can get r_final to update with itself?
This is my main code, the part in question is under the comment -- next state logic:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity serial_square is
port(
clk, reset: in std_logic;
q: out std_logic_vector (3 downto 0));
end serial_square;
architecture behavioral of serial_square is
signal r_reg : unsigned (3 downto 0) := "0000";
signal r_next : unsigned (3 downto 0);
signal r_2i : unsigned (3 downto 0);
signal r_min1 : unsigned (3 downto 0);
shared variable r_final : unsigned := "0000";
begin
-- register
process(clk,reset)
begin
if (reset='1') then
r_reg <= (others => '1');
elsif (clk'event and clk='1') then
r_reg <= r_final;
end if;
end process;
-- next state logic
r_next <= r_reg +1; -- r_reg + 1
r_2i <= r_next(2 downto 0) & '0'; -- multiply by 2
r_min1 <= r_2i - 1; -- minus one
r_final := r_min1 + r_final; -- add r_min1 to r_final, output should be the count r_next, squared.
--output logic
q <= std_logic_vector(r_reg);
end behavioral;
The update of r_final must be in the clocked process, so the next value is generated through a synchronous (clocked) update, since this is the structure that matches the available hardware.
Shared variables can't be synthesized, but is a feature only used for test benches.
Related
I will take two 1024-bit unsigned integers through serial communication ( 8-bit by 8-bit), convert ASCII to binary, then multiply them to form an output of 2048-bit. The main problem that I have to do multiplication operation with a very small-area FPGA board ( BASYS 2).
The multiplication speed is not an important criteria for me, I can wait a relatively long time ( ~ 1 sec ) to get the correct multiplication result.
Here is the resources information of my FPGA:
https://reference.digilentinc.com/_media/basys3:basys3_ss.pdf
What is a simple and area-effective way to do this?
a 1024-bit to 1024-bit adder takes alone around %53 of my area usage!
I assume you are certain that a true 1024 x 1024 multiplier really is needed (in many applications, something much cheaper will suffice). Maybe this is stating the obvious, but as a starting point I would try a very simple shift-add. Something like this would work (and I'm sure you can optimize it further to meet your needs):
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity wide_mult is
generic (
A_BITS : positive := 1024;
B_BITS : positive := 1024
);
port (
clk : in std_logic;
-- Input
in_valid : in std_logic;
in_a : in unsigned(A_BITS-1 downto 0);
in_b : in unsigned(B_BITS-1 downto 0);
-- Output
out_valid : out std_logic;
out_prod : out unsigned(A_BITS+B_BITS-1 downto 0)
);
end wide_mult;
architecture rtl of wide_mult is
signal shifted_a : unsigned(A_BITS-1 downto 0);
signal shifted_b : unsigned(A_BITS+B_BITS-1 downto 0);
signal progress : std_logic_vector(A_BITS-1 downto 0);
signal sum : unsigned(A_BITS+B_BITS-1 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
-- Cycle 1
if in_valid = '1' then
-- Initialize
shifted_a <= in_a;
shifted_b <= resize(in_b, A_BITS+B_BITS);
progress <= std_logic_vector(to_unsigned(1, A_BITS));
else
-- Shift
shifted_a <= shift_right(shifted_a, 1);
shifted_b <= shift_left(shifted_b, 1);
progress <= progress(A_BITS-2 downto 0) & '0';
end if;
-- Cycle 2 - Accumulate sum
out_valid <= progress(A_BITS-1);
if progress(0) = '1' then
-- Init sum
if shifted_a(0) = '0' then
sum <= (others => '0');
else
sum <= shifted_b;
end if;
elsif shifted_a(0) = '1' then
-- Accumulate
sum <= sum + shifted_b;
end if;
end if;
end process;
out_prod <= sum;
end rtl;
Your device is very small. If the simple shift-add doesn't even get close to fitting, then this might indicate that you need to change your approach. Since you have an enormous amount of time to do this sum, then perhaps you could offload it to a nearby CPU?
I'm having "Iteration limit reached" error in a simple FSM.
This is a part of of a bigger FSM I have to do for a class assignment, and I tracked the problem to this specific part.
The FSM will be controlling a counter, the state IDLE waits for inputs, ZERO sets the counter to zero, and the INCREMENT state increments the counter by one.
When simulating, the error occurs at the first time the input "inc" is high and the clock rises.
If I change the statement "temp := temp + 1;" for "temp := anything" the error stops. I really don't know what can be wrong, as for what I have found this error occurs when changing signals in the process sensitivity list inside the process itself.
I'm using Quartus II for the simulation.
Sorry for english mistakes.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.all;
entity fsm is
port
(
clock: in std_logic;
reset: in std_logic;
inc: in std_logic;
count: out std_logic_vector (13 downto 0);
cur_state: out std_logic_vector (1 downto 0)
);
end fsm;
architecture behaviour of fsm is
type state_type is (IDLE, INCREMENT, ZERO);
signal PS, NS: state_type;
begin
sync_proc: process (clock, reset)
begin
if (reset = '1') then
PS <= ZERO;
elsif (rising_edge(clock)) then
PS <= NS;
end if;
end process sync_proc;
comb_proc: process (PS, inc)
variable temp: unsigned (13 downto 0);
begin
case PS is
when IDLE =>
if (inc = '1') then
NS <= INCREMENT;
else
NS <= IDLE;
end if;
when INCREMENT =>
temp := temp + 1;
NS <= IDLE;
when ZERO =>
temp := "00000000000000";
NS <= IDLE;
when others =>
NS <= IDLE;
end case;
count <= std_logic_vector(temp);
end process comb_proc;
with PS select
cur_state <= "00" when IDLE,
"01" when INCREMENT,
"10" when ZERO,
"11" when others;
end behaviour;
You have a very serious CONCEPTUAL mistake in your case statement. Because it produces a combinational circuit (the combinational part of your FSM), it does not have memory, so it can't implement the equation "temp := temp + 1" (because, having no memory, it doesn't know what the value of temp is).
You can see more about this in chapter 11 of "Finite State Machines in Hardware...", by V.Pedroni, published by MIT.
I'm working in this school project.
I have two std_logic_vector (31 downto 0) A and B, and I have a variable type std_logic_vector (32 downto 0) and I want to add A+B and put the result in my std_logic_vector with 32 bits.
This is my design:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
use ieee.std_logic_arith.all;
entity Ej3 is
Port ( A : in STD_LOGIC_VECTOR (31 downto 0);
B : in STD_LOGIC_VECTOR (31 downto 0);
S : out STD_LOGIC_VECTOR (31 downto 0);
AluOp : in STD_LOGIC_VECTOR (3 downto 0);
COut : out STD_LOGIC;
Z : out STD_LOGIC;
OFL : out STD_LOGIC);
end Ej3;
architecture Behavioral of Ej3 is
begin
process(AluOp)
variable Temp: STD_LOGIC_VECTOR (32 downto 0);
begin
Temp := A+B;
And I have this error: found '0' definitions of operator "+", cannot determine exact overloaded matching definition for "+"
Can someone help??
First of all you've included the standard library numeric_std and the nonstandard library std_logic_arith together. They conflict with each other so get rid of std_logic_arith.
Both of those packages implement arithmetic using the unsigned and signed types. It is strongly recommend that you use these types if you want to do arithmetic on vectors. It makes it explicitly clear that you want them interpreted in a numeric context. There is no "+" operator defined for the std_logic_vector type implemented in std_logic_1164 which is why you get an error. You can augment that type with arithmetic operators in VHDL-2008 by also including numeric_std_unsigned. Again, it is better to just use the traditional unsigned type:
A : in unsigned(31 downto 0);
B : in unsigned(31 downto 0);
...
process(AluOp)
variable temp : unsigned(32 downto 0);
begin
temp := resize(A, temp'length) + B;
The length of the left and right sides of the assignment have to match so first resize the A signal, expanding it to 33 bits before adding the 32-bit signal B.
Quite new to VHDL here, so I'm not entirely sure if this is feasible at all, but here goes:
In my test code for some RAM, I have 2 8-bit std_logic_vector variables wdata_a_v and wdata_b_v. This is all I need for the current setup, but if the ratio of read to write data length changes, I will need more variables of the name wdata_*_v. I'm trying to write the code generically so that it will function for any amount of these variables, but I don't want to declare 26 of them in the code when I will likely only need a few.
It would be nice if there was a way to declare a variable like so:
variable wdata_*_v : std_logic_vector (7 downto 0);
that would, behind the scenes, declare all of the variables that fit this framework so that I could write a loop without worrying about running out of variables.
If there's a way to write a function or procedure etc. to make this work, that would be excellent.
Yes, you can go with a 2d array, recipe:
entity TestHelper is
generic (n: natural range 2 to 255 := 8);
end TestHelper;
architecture behavioral of TestHelper is
type array2d is array (n-1 downto 0) of std_logic_vector(7 downto 0);
begin
process
variable a : array2d;
begin
a(0)(0) := '0';
end process;
end architecture behavioral;
EDIT: Now to use it and create similar code for each of wdata_*_v:
process
variable wdata_v : array2d;
begin
someLabel: for i in 0 to n-1 generate
wdata_v(i)(0) := '0';
x <= y and z;
...
end generate;
x <= '1';
...
anotherLabel: for i in 1 to n generate
...
end generate;
...
end process;
I would like to set bits of a std_logic_vector separately in order to easily set comments for individual bits or group of bits. Here is what I have:
signal DataOut : std_logic_vector(7 downto 0);
...
DataOut <= ( 5=>'1', -- Instruction defined
4=>'1', -- Data length control bit, high=8bit bus mode selected
3=>'1', -- Display Line Number ctrl bit, high & N3 option pin to VDD=3 lines display
2=>'0', -- Double height font type control byte, not selected
1 downto 0=>"01", -- Select Instruction table1
others=>'0' -- for bits 6,7
);
However, I've a problem with the "downto" statement, I get the following error using Xilinx ISE:
Type std_ulogic does not match with a string litteral
Any solution to avoid using the equivalent
1=>'0',
0=>'1',
and to allow me to set bits by block?
The assignment X downto Y => 'A' is correct when A is a element of array. For example, this snippet is correct:
1 downto 0 => '1',
And this snippet is wrong:
1 downto 0 => "01",
Therefore, your assignment is illegal. As your code, you can assign as:
DataOut <= ( 5 downto 3 =>'1',
2 downto 1 =>'0',
0 => '1',
others=>'0'
);
If you want to access/assign by a feild of array, you can use concatenation:
DataOut <= Something_0 & Something_1 & "01";
While Something_* is std_logic_vector
Another answer is concatenation using '&', which loses the clarity of named association, though you can recover some of the self-documentation with named constants
constant Instr_Defined : std_ulogic := '1';
constant Bus_8_Bit : std_ulogic := '1';
DataOut <= "00" & Instr_Defined
& Bus_8_Bit
& '1' -- description
& '0' -- ditto
& "01";
Another answer is to write a function to create instructions : this can make the main flow very simple and clear, while keeping the instruction encodings entirely separate and in a single place, e.g. in a package used wherever you need to know the instruction formats (perhaps in an assembler as well as the CPU)
DataOut <= Encode_Instruction(Instr_Defined, Bus_8_Bit, Font_Mode);
It's OK to use any of the preceding techniques, however verbose, in the function body. The more explicit and detailed the better; it isn't cluttering up the main design so you'll rarely look at it unless changing instruction formats.
do this:
DataOut(7 downto 6)<="00";
DataOut(5)<='1';
DataOut(4)<='1';
DataOut(3)<='1';
DataOut(2)<='1';
DataOut(1 downto 0)<="01";