I have about six errors but they are all the same.
The error goes as such: near "?": syntax error, unexpected '?'
I've been trying to figure out how to fix this and I've looked at other problems in stackoverflow relating to this problem but to no avail. At first I thought it was how I was formatting my ternary statements but that wasn't it. So what could the prroblem be?
Code:
always_ff#(posedge clk, posedge reset)
if (reset) state <= S0;
else state <= nextstate;
always_comb
case (state)
S0: OpCode1 ? nextstate <= S2 : nextstate <= S1;
S1: OpCode2 ? nextstate <= S8 : nextstate <= S4;
S2: OpCode2 ? nextstate <= S3 : nextState <= S9;
S3: nextstate <= S0;
S4: A ? nextstate <= S5 : nextstate <= S13;
S5: B ? nextstate <= S7 : nextstate <= S6;
S6: Binv ? nextstate <= S14 : nextstate <= S13;
S7: Binv ? nextstate <= S13 : nextstate <= S14;
endcase
Note S1 to S14 are part of an enum that holds 5 bits[4:0]. The rest are inputs.
I don't see the result of ternary operation being assigned to a register.
Try rewriting it as below:
nextstate = (OpCode1) ? S2 : S1;
Related
I wrote this Verilog code on modelSim.
module my_fsm (clock , reset , in , out);
input clock , reset , in;
output out;
wire clock , reset , in;
reg out;
reg [1:0] state; // state of the machine in case reset = 0
// A = 00 , B = 01 , C = 10 , D = don't care = 11
always #(posedge clock) begin
if (reset == 1'b1)
begin
state <= 2'b00;
out <= 1'b0;
end
else
begin
case (state)
2'b00:
out <= 1'b0;
if (in == 1'b1) state <= 2'b01;
2'b01:
out <= in;
if (in == 1'b0) state <= 2'b10;
if (in == 1'b1) state <= 2'b00;
2'b10:
out <= 1'b1;
if (in == 1'b0) state <= 2'b01;
default: out <= 1'bX;
endcase
end
end
endmodule
But the compiler is giving me this compilation errors:
** Error: (vlog-13069) C:/Users/michael/Documents/Logic Design/hw1/my_fsm .v(22): near "if": syntax error, unexpected if.
** Error: (vlog-13069) C:/Users/michael/Documents/Logic Design/hw1/my_fsm .v(27): near "2": syntax error, unexpected INTEGER NUMBER.
** Error: (vlog-13069) C:/Users/michael/Documents/Logic Design/hw1/my_fsm .v(30): near "default": syntax error, unexpected default.
I have looked up for those problems but couldn't find any solution for them.
Thank you,
Michael
Multiple statements in a branch of a case statement should be enclosed between begin and end. (Just like in an if statement, just like you've done in your if (reset == 1'b1) statement.)
so I seem to be having a problem in regards to flag signal getting asserted. So basically I am implementing i2c interface between 2 fpga's. My master will send over 50 bytes. On my slave side I want to store the byte coming in into an array. So I check when ever the whole byte is read and available i put it into an array. Now the problem is that after i fill up the whole array i want to assert a signal that should activate a process. My problem is that when the signal is asserted and the process is activated that that I am stuck in the idle loop forever, which confuses me because I was under the assumption that when i enter the process and check the flag signal assertion condition that it is suppose to be high. So is the problem that my signal is not activating the process or is my problem that the by the time i check the flag assertion conditional that the flag already went back to 0?
I have attached some code:
signal i : integer range 0 to 49 := 0;
type field_array is array(0 to 49) of std_logic_vector(7 downto 0);
begin
process(clk,rst)
begin
if( rst = '1') then
i <= 0;
elsif (rising_edge(clk)) then
if(data_available = '1') then
array_of_data(i) <= Master_Data;
i <= i + 1;
end if;
if(i = 49) then
i <= 0; -- reset index back to zero
end if;
end if;
end process;
flag <= '1' when i = 49 else '0';
process(state,flag)
begin
next_state <= state;
case (state) is
when idle =>
if(flag = '1') then
next_state <= Send_data;
end if;
when Send_data =>...
There is a bounds check failure on your assignment, i <= i+1;. It is trying to evaluate it before the check that is performed later (if i=49...).
Change the synchronous part of you code to:
elsif rising_edge(clk) then
if data_available = '1' then
array_of_data(i) <= Master_Data;
if i = 49 then
i <= 0;
else
i <= i + 1;
end if;
end if;
end if;
EDIT:
You can see that the flag is being asserted and the state changes here.
Further EDIT:
Consider making your state machine synchronous and removing the next_state signal. eg.
type state_t is (idle_s, send_s, others_s);
signal state : state_t := idle_s;
...
process(clk,rst)
begin
if rst = '1' then
-- rst
elsif rising_edge(clk) then
case (state) is
when idle_s =>
if flag = '1' then
state <= send_s;
else
state <= idle_s;
end if;
when send_s =>
-- Do stuff
when others =>
-- stuff
end case;
end if;
end process;
If you want to assign your outputs as soon as your state changes, you can use a two process state machine. One of the processes (synchronous) is used to control state transitions, the other is used to control the output (combinational). You would effectively have another process similar to the first:
process(state)
begin
case state is
when idle_s =>
my_output <= '0';
when send_s =>
-- Assign output as necessary
my_output <= '1';
when others =>
--assign output
end case;
end process;
An example is shown here.
So I'm trying to design a 'vending machine' sequential circuit in Vivado for the ZYBO FPGA board. However, every time I try to get past the Implementation stage I get a bunch of errors, the main one being
[Place 30-58] IO placement is infeasible. Number of unplaced terminals (1) is greater than
number of available sites (0).
The following Groups of I/O terminals have not sufficient capacity:
IO Group: 0 with : SioStd: LVCMOS18 VCCO = 1.8 Termination: 0 TermDir: In RangeId: 1
has only 0 sites available on device, but needs 1 sites.
Term: clk
I did try the Auto I/O planning, but all that ended up doing was removing the pin constraints. It got through implementation at that point but then of course couldn't generate the bit stream because none of the ports were mapped to pins.
Here's my VHDL design
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY des_src IS
PORT (
reset : IN std_logic;
clk : IN std_logic;
QDN : IN std_logic_vector(2 DOWNTO 0);
PC : OUT std_logic_vector(1 DOWNTO 0)
);
END des_src;
ARCHITECTURE behavioral OF des_src IS
TYPE statetype IS (Start, Five, Ten, Fifteen, Twenty, Twentyfive, Thirty, Thirtyfive, Fourty, Fourtyfive);
SIGNAL currentstate, nextstate : statetype;
BEGIN
fsm1: PROCESS (QDN, currentstate)
BEGIN
CASE currentstate IS
WHEN Start =>
PC <= "00";
CASE QDN IS
WHEN "000" =>
nextstate <= Start;
WHEN "001" =>
nextstate <= Five;
WHEN "010" =>
nextstate <= Ten;
WHEN "100" =>
nextstate <= Twentyfive;
WHEN OTHERS =>
nextstate <= Start;
END CASE;
WHEN Five =>
PC <= "00";
CASE QDN IS
WHEN "000" =>
nextstate <= Five;
WHEN "001" =>
nextstate <= Ten;
WHEN "010" =>
nextstate <= Fifteen;
WHEN "100" =>
nextstate <= Thirty;
WHEN OTHERS =>
nextstate <= Start;
END CASE;
WHEN Ten =>
PC <= "00";
CASE QDN IS
WHEN "000" =>
nextstate <= Ten;
WHEN "001" =>
nextstate <= Fifteen;
WHEN "010" =>
nextstate <= Twenty;
WHEN "100" =>
nextstate <= Thirtyfive;
WHEN OTHERS =>
nextstate <= Start;
END CASE;
WHEN Fifteen =>
PC <= "00";
CASE QDN IS
WHEN "000" =>
nextstate <=Fifteen;
WHEN "001" =>
nextstate <= Twenty;
WHEN "010" =>
nextstate <= Twentyfive;
WHEN "100" =>
nextstate <= Fourty;
WHEN OTHERS =>
nextstate <= Start;
END CASE;
WHEN Twenty =>
PC <= "00";
CASE QDN IS
WHEN "000" =>
nextstate <= Twenty;
WHEN "001" =>
nextstate <= Twentyfive;
WHEN "010" =>
nextstate <= Thirty;
WHEN "100" =>
nextstate <= Fourtyfive;
WHEN OTHERS =>
nextstate <= Start;
END CASE;
WHEN Twentyfive =>
PC <= "10";
nextstate <= Start;
WHEN Thirty =>
PC <= "01";
nextstate <= Twentyfive;
WHEN Thirtyfive =>
PC <= "01";
nextstate <= Thirty;
WHEN Fourty =>
PC <= "01";
nextstate <= Thirtyfive;
WHEN Fourtyfive =>
PC <= "01";
nextstate <= Fourty;
END CASE;
END PROCESS;
fsm2: PROCESS (reset, clk)
BEGIN
IF (reset = '0') THEN
currentstate <= Start;
ELSIF (clk'EVENT) AND (clk = '1') THEN
currentstate <= nextstate;
END IF;
END PROCESS;
END behavioral;
Here are my constraints
##Buttons
##IO_L20N_T3_34
set_property IOSTANDARD LVCMOS33 [get_ports {QDN[0]}]
set_property PACKAGE_PIN R18 [get_ports {QDN[0]}]
##IO_L24N_T3_34
set_property IOSTANDARD LVCMOS33 [get_ports {QDN[1]}]
set_property PACKAGE_PIN P16 [get_ports {QDN[1]}]
##IO_L18P_T2_34
set_property IOSTANDARD LVCMOS33 [get_ports {QDN[2]}]
set_property PACKAGE_PIN V16 [get_ports {QDN[2]}]
##IO_L7P_T1_34
set_property IOSTANDARD LVCMOS33 [get_ports reset]
set_property PACKAGE_PIN Y16 [get_ports reset]
##LEDs
##IO_L23P_T3_35
set_property IOSTANDARD LVCMOS33 [get_ports {PC[0]}]
set_property PACKAGE_PIN M14 [get_ports {PC[0]}]
##IO_L23N_T3_35
set_property IOSTANDARD LVCMOS33 [get_ports {PC[1]}]
set_property PACKAGE_PIN M15 [get_ports {PC[1]}]
create_clock -period 10.000 -name clk -waveform {0.000 5.000} [get_ports clk]
set_input_delay -clock [get_clocks clk] -min -add_delay 0.000 [get_ports {QDN[*]}]
set_input_delay -clock [get_clocks clk] -max -add_delay 0.000 [get_ports {QDN[*]}]
set_input_delay -clock [get_clocks clk] -min -add_delay 0.000 [get_ports reset]
set_input_delay -clock [get_clocks clk] -max -add_delay 0.000 [get_ports reset]
set_output_delay -clock [get_clocks clk] -min -add_delay 0.000 [get_ports {PC[*]}]
set_output_delay -clock [get_clocks clk] -max -add_delay 0.000 [get_ports {PC[*]}]
I'm using Vivado 2015.2 and designing for the ZYBO development board.
Any and all help is appreciated.
Edit 8/26/15
Alright, I got my code working for the most part. I was able to use
set_property PACKAGE_PIN L16 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
create_clock -period 10.000 -name clk -waveform {0.000 5.000} [get_ports clk]
for my clock. However, this clock is way faster than I want it to be (125MHz), so I know I have to use clock division and in the constraint file generate a clock, but do I need to assign the generated clock to a pin? And does anyone have any tips on how to include the clock divider in my current vhdl code? Do I just make it another process, and add another port, or is it more complicated than that?
You did not assign a pin to the clk primary. I guess Vivado decides that a 1.8V LVCMOS input is needed for it (probably the default) but there are no LVCMOS 1V8 user pins available on the Zybo: the only 1V8 bank is 501 and it is already fully used by Ethernet, USB OTG, SD card, UART and press-buttons. As you probably told Vivado that you are using the Zybo, it cannot solve this issue alone.
So, if you have an external clock source, wire it to one of the pmod connectors, declare the corresponding pin as LVCMOS3V3 and assign it to clk. Else, if you want your clock to be driven by the processing system, you must explicitly wire one of the 4 FCLK PS-to-PL clocks to the clk input of your design.
The easiest way to do this, in my opinion, is to turn your design into an IP (see Vivado documentation), instantiate it in a block design, add a processing system and the primary I/Os you need and do the wiring.
I'm new to VHDL and I thought I could try to make a slave SPI device as training, but it's not working quite as expected. Below my current code. It's compiles and upload just fine, but it's not working as intended. Right now I have the leds connected to the signal "bitnumber", bitnumber is supposed to increment on each rising edge of CLK and then reset to zero when the SS pin is pulled LOW (indicating that the transfer is complete), but it doesn't do that. I've connected my Altera DE0-nano to my arduino which is simply pulling the SS LOW, sends four clock pulses and then pulls the SS back high, I've put a 1s delay between each transition. The leds on my altera board does change it's pattern every second, but it does so on both rising and falling edge of the clock, also the led pattern seems completely random, even showing some leds in a dimmed state. The leds become black when the SS pin goes back HIGH though, that's good.
enter code here
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SPI2 is
PORT (LED : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
GPIO_0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0));
end SPI2;
architecture SPI2_beh of SPI2 is
signal SPIdataregister : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal bitnumber : STD_LOGIC_VECTOR(7 DOWNTO 0);
begin
LED <= bitnumber;
process(GPIO_0(5), GPIO_0(3))
begin
if ((GPIO_0(5)) = '1') then
bitnumber <= (bitnumber + '1');
end if;
if ((GPIO_0(3)) = '1') then
bitnumber <= "00000000";
end if;
end process;
process(bitnumber)
begin
case bitnumber is
when "00000001" => SPIdataregister(0) <= GPIO_0(7);
when "00000010" => SPIdataregister(1) <= GPIO_0(7);
when "00000011" => SPIdataregister(2) <= GPIO_0(7);
when "00000100" => SPIdataregister(3) <= GPIO_0(7);
when "00000101" => SPIdataregister(4) <= GPIO_0(7);
when "00000110" => SPIdataregister(5) <= GPIO_0(7);
when "00000111" => SPIdataregister(6) <= GPIO_0(7);
when "00001000" => SPIdataregister(7) <= GPIO_0(7);
when others => SPIdataregister <= SPIdataregister;
end case;
end process;
end SPI2_beh;
enter code here
I would start by changing the main process to:
process(GPIO_0(5), GPIO_0(3))
variable change_flag : STD_LOGIC := 1;
begin
if GPIO_0(3) = '1' then
bitnumber <= "00000000";
else
if GPIO_0(5) = '0' --btw here, GPIO_0(3) = '0' also
change_flag := '1';
else --btw here, GPIO_0(3) = '0' and GPIO_0(5) = '1'
if change_flag = '1' then
bitnumber <= bitnumber + 1;
change_flag := '0';
end if;
end if;
end if;
end process;
The variable change_flag introduces memory, to ensure the process only reacts once to specifically a rising edge of GPIO_0(5). Without memory implemented like this, you could get the desired effect by having two processes: one dependent on GPIO_0(5) and one dependent on GPIO_0(3). The risk then is of both changing at the same time and causing a conflict: two signals trying to control/change the same output. The above way is better and should be reliable for your purposes.
Secondly, increment bitnumber using
bitnumber <= bitnumber + 1;
note, use the 1 without the quotes. The quotes indicate binary '1' and '0' from what I understand.
Good luck!!
Thanks to all your input, I implemented your suggestions, however the problem remains the same. The result in simulation works fine, but the hardware
outputs something different. Just to briefly recap, I have two ctrl signals that determine the behaviour of the entity:
GET (ctrl = "00000000") sets register tx to input of op1
SH1_L (ctrl = "00000001") res := (op1 << 1) | tx;
tx := tx >> 31;
Here is the VHDL code:
library ieee;
use ieee.std_logic_1164.all;
entity test is
port
(
op1 : in std_logic_vector(31 downto 0); -- Input operand
ctrl : in std_logic_vector(7 downto 0); -- Control signal
clk : in std_logic; -- clock
res : out std_logic_vector(31 downto 0) -- Result
);
end;
architecture rtl of test is
type res_sel_type is (GET, SH1_L);
constant Z : std_logic_vector(31 downto 0) := (others => '0');
signal res_sel : res_sel_type;
signal load : std_logic := '0';
signal shl : std_logic := '0';
signal tx : std_logic_vector(31 downto 0) := (others => '0');
signal inp1 : std_logic_vector(31 downto 0) := (others => '0');
begin
dec_op: process (ctrl, op1)
begin
res_sel <= GET;
load <= '0';
shl <= '0';
inp1 <= ( others => '0');
case ctrl is
-- store operand
when "00000000" =>
inp1 <= op1;
load <= '1';
res_sel <= GET;
-- 1-bit left-shift with carry
when "00000001" =>
inp1 <= op1;
shl <= '1';
res_sel <= SH1_L;
when others =>
-- Leave default values
end case;
end process;
sel_out: process (res_sel, inp1, tx)
begin
case res_sel is
when SH1_L =>
res <= ( inp1(30 downto 0) & '0' ) or tx;
when others =>
res <= (others => '0');
end case;
end process;
sync: process(clk)
begin
if clk'event and clk = '1' then
if load = '1' then
tx <= op1;
elsif shl = '1' then
tx <= Z(30 downto 0) & op1(31);
end if;
end if;
end process;
end rtl;
TESTPROGRAM
GET 0 (this sets tx <= 0 )
SH1_L 0xfedcba90 exp. output: 0xfdb97520 act. output = 0xfdb97521
SH1_L 0x7654321f exp. output: 0xeca8643f act. output = 0xeca8643f
SH1_L 0x71234567 exp. output: 0xe2468ace act. output = 0xe2468ace
As you can see, the last bit is wrong for the first SH1_L operation. The first SH1_L operation produces a carry for the NEXT SH1_L operation since
the MSB is set to one of the input, however, it seems that this carry is already considered in the current SH1_L operation, which is wrong (tx should be zero).
I checked the synthesis report and there are no latches, so I am a bit clueless and almost desperate what is going wrong here. I use Xilinx ISE 12.1 for
synthesis, could there be a problem because I do not have a reset signal in my architecture, that the wrong kind of latches are instantiated?
Many thanks for further helpful comments to solve this issue,
Patrick
Unlike RTL simulation, real-life timing of inputs and clocks is not ideal. For example, the clock tree might have a longer delay than input buffers or vice versa. Did you take this into account?