place_design Error for clock constraint VHDL Vivado FPGA - syntax-error

Question

So I'm trying to design a 'vending machine' sequential circuit in Vivado for the ZYBO FPGA board. However, every time I try to get past the Implementation stage I get a bunch of errors, the main one being
[Place 30-58] IO placement is infeasible. Number of unplaced terminals (1) is greater than
number of available sites (0).
The following Groups of I/O terminals have not sufficient capacity:
IO Group: 0 with : SioStd: LVCMOS18 VCCO = 1.8 Termination: 0 TermDir: In RangeId: 1
has only 0 sites available on device, but needs 1 sites.
Term: clk
I did try the Auto I/O planning, but all that ended up doing was removing the pin constraints. It got through implementation at that point but then of course couldn't generate the bit stream because none of the ports were mapped to pins.
Here's my VHDL design
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY des_src IS
PORT (
reset : IN std_logic;
clk : IN std_logic;
QDN : IN std_logic_vector(2 DOWNTO 0);
PC : OUT std_logic_vector(1 DOWNTO 0)
);
END des_src;
ARCHITECTURE behavioral OF des_src IS
TYPE statetype IS (Start, Five, Ten, Fifteen, Twenty, Twentyfive, Thirty, Thirtyfive, Fourty, Fourtyfive);
SIGNAL currentstate, nextstate : statetype;
BEGIN
fsm1: PROCESS (QDN, currentstate)
BEGIN
CASE currentstate IS
WHEN Start =>
PC <= "00";
CASE QDN IS
WHEN "000" =>
nextstate <= Start;
WHEN "001" =>
nextstate <= Five;
WHEN "010" =>
nextstate <= Ten;
WHEN "100" =>
nextstate <= Twentyfive;
WHEN OTHERS =>
nextstate <= Start;
END CASE;
WHEN Five =>
PC <= "00";
CASE QDN IS
WHEN "000" =>
nextstate <= Five;
WHEN "001" =>
nextstate <= Ten;
WHEN "010" =>
nextstate <= Fifteen;
WHEN "100" =>
nextstate <= Thirty;
WHEN OTHERS =>
nextstate <= Start;
END CASE;
WHEN Ten =>
PC <= "00";
CASE QDN IS
WHEN "000" =>
nextstate <= Ten;
WHEN "001" =>
nextstate <= Fifteen;
WHEN "010" =>
nextstate <= Twenty;
WHEN "100" =>
nextstate <= Thirtyfive;
WHEN OTHERS =>
nextstate <= Start;
END CASE;
WHEN Fifteen =>
PC <= "00";
CASE QDN IS
WHEN "000" =>
nextstate <=Fifteen;
WHEN "001" =>
nextstate <= Twenty;
WHEN "010" =>
nextstate <= Twentyfive;
WHEN "100" =>
nextstate <= Fourty;
WHEN OTHERS =>
nextstate <= Start;
END CASE;
WHEN Twenty =>
PC <= "00";
CASE QDN IS
WHEN "000" =>
nextstate <= Twenty;
WHEN "001" =>
nextstate <= Twentyfive;
WHEN "010" =>
nextstate <= Thirty;
WHEN "100" =>
nextstate <= Fourtyfive;
WHEN OTHERS =>
nextstate <= Start;
END CASE;
WHEN Twentyfive =>
PC <= "10";
nextstate <= Start;
WHEN Thirty =>
PC <= "01";
nextstate <= Twentyfive;
WHEN Thirtyfive =>
PC <= "01";
nextstate <= Thirty;
WHEN Fourty =>
PC <= "01";
nextstate <= Thirtyfive;
WHEN Fourtyfive =>
PC <= "01";
nextstate <= Fourty;
END CASE;
END PROCESS;
fsm2: PROCESS (reset, clk)
BEGIN
IF (reset = '0') THEN
currentstate <= Start;
ELSIF (clk'EVENT) AND (clk = '1') THEN
currentstate <= nextstate;
END IF;
END PROCESS;
END behavioral;
Here are my constraints
##Buttons
##IO_L20N_T3_34
set_property IOSTANDARD LVCMOS33 [get_ports {QDN[0]}]
set_property PACKAGE_PIN R18 [get_ports {QDN[0]}]
##IO_L24N_T3_34
set_property IOSTANDARD LVCMOS33 [get_ports {QDN[1]}]
set_property PACKAGE_PIN P16 [get_ports {QDN[1]}]
##IO_L18P_T2_34
set_property IOSTANDARD LVCMOS33 [get_ports {QDN[2]}]
set_property PACKAGE_PIN V16 [get_ports {QDN[2]}]
##IO_L7P_T1_34
set_property IOSTANDARD LVCMOS33 [get_ports reset]
set_property PACKAGE_PIN Y16 [get_ports reset]
##LEDs
##IO_L23P_T3_35
set_property IOSTANDARD LVCMOS33 [get_ports {PC[0]}]
set_property PACKAGE_PIN M14 [get_ports {PC[0]}]
##IO_L23N_T3_35
set_property IOSTANDARD LVCMOS33 [get_ports {PC[1]}]
set_property PACKAGE_PIN M15 [get_ports {PC[1]}]
create_clock -period 10.000 -name clk -waveform {0.000 5.000} [get_ports clk]
set_input_delay -clock [get_clocks clk] -min -add_delay 0.000 [get_ports {QDN[*]}]
set_input_delay -clock [get_clocks clk] -max -add_delay 0.000 [get_ports {QDN[*]}]
set_input_delay -clock [get_clocks clk] -min -add_delay 0.000 [get_ports reset]
set_input_delay -clock [get_clocks clk] -max -add_delay 0.000 [get_ports reset]
set_output_delay -clock [get_clocks clk] -min -add_delay 0.000 [get_ports {PC[*]}]
set_output_delay -clock [get_clocks clk] -max -add_delay 0.000 [get_ports {PC[*]}]
I'm using Vivado 2015.2 and designing for the ZYBO development board.
Any and all help is appreciated.
Edit 8/26/15
Alright, I got my code working for the most part. I was able to use
set_property PACKAGE_PIN L16 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
create_clock -period 10.000 -name clk -waveform {0.000 5.000} [get_ports clk]
for my clock. However, this clock is way faster than I want it to be (125MHz), so I know I have to use clock division and in the constraint file generate a clock, but do I need to assign the generated clock to a pin? And does anyone have any tips on how to include the clock divider in my current vhdl code? Do I just make it another process, and add another port, or is it more complicated than that?

Answer 1

You did not assign a pin to the clk primary. I guess Vivado decides that a 1.8V LVCMOS input is needed for it (probably the default) but there are no LVCMOS 1V8 user pins available on the Zybo: the only 1V8 bank is 501 and it is already fully used by Ethernet, USB OTG, SD card, UART and press-buttons. As you probably told Vivado that you are using the Zybo, it cannot solve this issue alone.
So, if you have an external clock source, wire it to one of the pmod connectors, declare the corresponding pin as LVCMOS3V3 and assign it to clk. Else, if you want your clock to be driven by the processing system, you must explicitly wire one of the 4 FCLK PS-to-PL clocks to the clk input of your design.
The easiest way to do this, in my opinion, is to turn your design into an IP (see Vivado documentation), instantiate it in a block design, add a processing system and the primary I/Os you need and do the wiring.