Variables expansion in Make - variables

Question

Let us assume I have the following Makefile
N := 1
.PHONY : target_$(N)
target_$(N) :
#echo $(N)
N := 2
.PHONY : target_$(N)
target_$(N) :
#echo $(N)
The result is:
$ make target_1
2
$ make target_2
2
Is there any way of achieving what I want? My idea was to copy-paste a recipe using a variable as parameter. The variable has to be expanded in the target name and in the recipe for that target, perhaps it could appear in the dependencies too, but not for now. The problem is that recipe expansion seems to occur at the time of recipe execution, but I was expecting, and needing, it to occur at the same time that target expansion.

Answer 1

Another option is to use target-specific variables:
N := 1
.PHONY : target_$(N)
target_$(N) :
#echo $(N)
target_$(N) : N := $(N)

Answer 2

Instead of all the ugly nested function invocations, I'd say KEEP IT SIMPLE and use a command line variable as a parameter for just a single target.
target:
#echo ${N}
#if test ${N} -eq 1; then DO THIS; else DO THAT; fi
and call your Makefile with
make target N=1
That way you have all the power of the shell's control constructs. And your Makefile remains fully portable to non-GNU make.

Answer 3

I can achieve the result you want with automatic variables and a pattern rule:
target_%:
#echo $*
Output:
$ make target_1
1
$ make target_2
2
To make the value available in the prerequisites list you need the .SECONDEXPANSION special target:
.SECONDEXPANSION:
target_%: prerequisite_$$*
#echo $<
prerequisite_%:
#echo "do something here to build prerequisite nb.$*"
Output:
$ make target_1
do something here to build prerequisite nb.1
prerequisite_1

Answer 4

The expansion of make variables occurs when necessary. In target lines, such as target_$(N):, that occurs as the line is read. In command (recipe) lines, it occurs when the action is executed. Thus, you can change the value of N as the file is read, but the final value is the one that will be used when the command is executed, hence the value 2 appears twice. (Doing that will lead to confusion; don't use it in production makefiles.)
AFAIK, there isn't a way to change that behaviour. You can't freeze the macro set at the point where the command line is read. Some of the macros may not have been defined until after they were used in a command line, and you need to be able to change the values of the macros used by the default rules, etc.

Answer 5

I have found that the best way to do what I wanted was to stripe the parameter from the target names themselves:
TARGETS := target_1 target_2
.PHONY : $(TARGETS)
$(TARGETS) :
$(eval $#_N := $(subst target_,,$#))
#echo $($#_N)
If the target names become too complicated, one may programatically create them from the parameter set to start with.