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I got a pyomo concrete model with lots of variables and constraints.
Somehow, one of the variable inside my model violates one constraint, which makes my model infeasible:
WARNING: Loading a SolverResults object with a warning status into model=xxxx;
message from solver=Model was proven to be infeasible.
Is there a way to ask the solver, the reason of the infeasibility?
So for example, lets assume I got a variable called x, and if I define following 2 constraints, model will be ofc. infeasible.
const1:
x >= 10
const2:
x <= 5
And what I want to achieve that pointing out the constraints and variable which causes this infeasibility, so that I can fix it. Otherwise with my big model it is kinda hard to get what causing this infeasibility.
IN: write_some_comment
OUT: variable "x" cannot fulfill "const1" and "const2" at the same time.
Many solvers (including IPOPT) will hand you back the value of the variables at solver termination, even if the problem was found infeasible. At that point, you do have some options.
There is contributed code in pyomo.util.infeasible that might help you out. https://github.com/Pyomo/pyomo/blob/master/pyomo/util/infeasible.py
Usage:
from pyomo.util.infeasible import log_infeasible_constraints
...
SolverFactory('your_solver').solve(model)
...
log_infeasible_constraints(model)
I would not trust any numbers that the solver loads into the model after reporting "infeasible." I don't think any solvers come w/ guarantees on the validity of those numbers. Further, unless a package can divine the modeler's intent, it isn't clear how it would list the infeasible constraints. Consider 2 constraints:
C1: x <= 5
C2: x >= 10
X ∈ Reals, or Integers, ...
Which is the invalid constraint? Well, it depends! Point being, it seems an impossible task to unwind the mystery based on values the solver tries.
A possible alternate strategy: Load the model with what you believe to be a valid solution, and test the slack on the constraints. This "loaded solution" could even be a null case where everything is zero'ed out (if that makes sense in the context of the model). It could also be a set of known feasible solutions tried via unit test code.
If you can construct what you believe to be a valid solution (forget about optimal, just something valid), you can (1) load those values, (2) iterate through the constraints in the model, (3) evaluate the constraint and look for negative slack, and (4) report the culprits with values and expressions
An example:
import pyomo.environ as pe
test_null_case = True
m = pe.ConcreteModel('sour constraints')
# SETS
m.T = pe.Set(initialize=['foo', 'bar'])
# VARS
m.X = pe.Var(m.T)
m.Y = pe.Var()
# OBJ
m.obj = pe.Objective(expr = sum(m.X[t] for t in m.T) + m.Y)
# Constraints
m.C1 = pe.Constraint(expr=sum(m.X[t] for t in m.T) <= 5)
m.C2 = pe.Constraint(expr=sum(m.X[t] for t in m.T) >= 10)
m.C3 = pe.Constraint(expr=m.Y >= 7)
m.C4 = pe.Constraint(expr=m.Y <= sum(m.X[t] for t in m.T))
if test_null_case:
# set values of all variables to a "known good" solution...
m.X.set_values({'foo':1, 'bar':3}) # index:value
m.Y.set_value(2) # scalar
for c in m.component_objects(ctype=pe.Constraint):
if c.slack() < 0: # constraint is not met
print(f'Constraint {c.name} is not satisfied')
c.display() # show the evaluation of c
c.pprint() # show the construction of c
print()
else:
pass
# instantiate solver & solve, etc...
Reports:
Constraint C2 is not satisfied
C2 : Size=1
Key : Lower : Body : Upper
None : 10.0 : 4 : None
C2 : Size=1, Index=None, Active=True
Key : Lower : Body : Upper : Active
None : 10.0 : X[foo] + X[bar] : +Inf : True
Constraint C3 is not satisfied
C3 : Size=1
Key : Lower : Body : Upper
None : 7.0 : 2 : None
C3 : Size=1, Index=None, Active=True
Key : Lower : Body : Upper : Active
None : 7.0 : Y : +Inf : True
Do input and output ports in VHDL behave like flip-flops, i.e. are they updated on a rising or falling edge of a clock? Here is an example of what I mean.
entity main is
port(
clk : in std_logic; -- FPGA clock
x : in std_logic; -- input signal
y : out std_logic -- sampled input signal
);
end entity main;
architecture RTL of main is
signal y_q : std_logic;
begin
y <= y_q; -- set the output
copy : process(clk, x) is
variable y_d : std_logic;
begin
y_d := x; -- continuously sample x
if rising_edge(clk) then -- synchronous logic
y_q <= y_d; -- update flip-flop
end if;
end process copy;
end architecture RTL;
The program above simply samples the input signal x, and sends it to the output y. The signal y_q is the sampled input signal x, whereas a sample is taken on every rising edge of a clock clk. However, I'm confused about the y signal - is that signal completely the same as y_q, or it is delayed by one clock cycle?
y <= y_q just "wires up" y to y_q. There's no extra logic implied, so there's no delay.
Alternatively, you can just look at the RTL generated for this module! The screenshot below is from Xilinx ISE. ("fd" is the Xilinx name for a D-type flip-flop.)
Because you asked.
The code below is accepted by Intel/Altera and Xilinx synthesis.
entity main is
port(
clk : in std_logic; -- FPGA clock
x : in std_logic; -- input signal
y : out std_logic -- sampled input signal
);
end entity main;
architecture RTL of main is begin
y <= x when rising_edge(clk);
end architecture RTL;
Yes, you can use when. You just cannot use it in a process before 2008.
As for you question, is signal y the same as signal y_q, the answer is YES.
y <= y_q;
is a cocurrent assignment out of any processes, it just says the two signals y and y_q should be connected together, so of course, they are the same.
You should not write a register in this style, although your code seems right logically. You could check xilinx XST user guide, it will tell you how to describe a few kinds of registers.
My knowledge of Micro-controllers is fairly limited at this point, but here goes.
I have an Led Driver PT6959 which I'm trying to interface with. Data is read serially by the Driver IC on the input CLK rising edge once the STB input line goes low.
My question is, how do I know what the input CLK frequency should be?
Does it matter? Or should it be the same as the Led Driver OSC Pin frequency?
I've read the datasheet but can't find any reference to specifying an input CLK frequency.
If your microcontroller has a SPI port, connect as follows:
DIN <-- SPI-MOSI
CLK <-- SPI-CLK
STB <-- CS (often just a GPIO rather than a dedicated SPI chipselect)
The SPI peripheral will then do most of the work for you. Most SPI peripherals allow different combinations of polarity and phase known as modes:
Mode CPOL CPHA
0 0 0
1 0 1
2 1 0
3 1 1
The PT6959 operates in mode 3.
The clock rate is probably not be critical. If you are bit-banging it rather than using SPI, it need not even be periodic or fixed - it is the state of DIN on rising and falling edges that is critical - not the frequency. The device will have some maximum rate - the data sheet specifies this in terms of minimum mark/space widths of >=400ns, assuming a 50% mark:space, that would correspond to 1.25MHz, but there is little benefit in operating at the maximum speed.
I have found it finally here the bigger datasheet fourteen (14) pages, not three.
So the time constraints for this signal as below,
PW CLK (Clock Pulse Width) ≥ 400ns
t setup (Data Setup Time) ≥ 100ns
t CLK-STB (Clock - Strobe Time) ≥ 1μs
t TZH (Rise Time) ≤ 1μs
t TZL < 1μs
V1.7
PW STB (Strobe Pulse Width) ≥ 1μs
t hold (Data Hold Time) ≥ 100ns
t THZ (Fall Time) ≤ 10μ
fosc=Oscillation Frequency
t TLZ < 10μs
As you can see the minimum clock pulse can be as 400ns which means the maximum clock frequency can found as 1/(2x400x10-9) = 1250000Hz (1.25Mhz)
Other calculations you can do the same way. But, yes, it is everything needed better covered at time-diagrams, which are given in the document above. I place them here just in case the link can die one day.
I'm trying to make a mod-12 counter in Verilog using 4 D-FFs. I've actually come up with two implementations, one of which works as intended (but is really bad practice IRL), and the other does not work as intended. The following is the ideal(correct) output generated from my "bad" implementation.
And the following is what's generated from the module I'm having trouble with.
Here is the module that generated the top image:
module Mod12Counter(q, clk, rstIn0);
output [3:0] q;
input clk, rstIn0;
DF DF0(q[0], qBar0, qBar0, clk, rst),
DF1(q[1], qBar1, qBar1, qBar0, rst),
DF2(q[2], qBar2, qBar2, qBar1, rst),
DF3(q[3], qBar3, qBar3, qBar2, rst);
and and0(test, q[2], q[3]);
or or0 (rst, rstIn0, test);
endmodule
And here is the module that generated the bottom image:
module Mod12Counter(q, clk, rst);
output [3:0] q;
input clk, rst;
and and0(d1In0, q[1], qBar0),
and1(d1In1, qBar1, q[0]),
and2(d2In0, q[2], qBar1),
and3(d2In1, qBar3, qBar2, q[1], q[0]),
and4(d2In2, q[2], qBar0),
and5(d3In0, q[3], qBar1),
and6(d3In1, q[2], q[1], q[0]),
and7(d3In2, q[3], qBar0);
or or0(d1, d1In0, d1In1),
or1(d2, d2In0, d2In1, d2In2),
or2(d3, d3In0, d3In1, d3In2);
DF DF0(q[0], qBar0, qBar0, clk, rst),
DF1(q[1], qBar1, d1, qBar0, rst),
DF2(q[2], qBar2, d2, qBar1, rst),
DF3(q[3], qBar3, d3, qBar2, rst);
endmodule
What's really weird is these two modules should behave exactly the same way. The only difference is one is just made using my gut feelings and the other one is generated by deriving equations from state tables. From what I know, the bottom module is much more preferable to use IRL.
So far the problem I'm seeing is q[2] and q[3] don't get triggered at all in the bottom module. I've tried using BUS assignment as you see now and I've also tried not using BUS assignment.
I've spent MANY hours on this, and I would really appreciate it if you could help me debug the module, point at the right direction, or tell me a better place to go for things like this.
If q[2] is never going high, the first thing you should look at is to understand why the input to DF2 is not ever going high at the point when the clock rises.
Looking at the inputs to see what drives d2, I see these three lines:
and2(d2In0, q[2], qBar1),
and3(d2In1, qBar3, qBar2, q[1], q[0]),
and4(d2In2, q[2], qBar0),
Obviously and2 and and4 cannot help you here, because they require q[2] to be true in order to be true, so we can throw those out, leaving just these lines to look at:
and3(d2In1, qBar3, qBar2, q[1], q[0]),
or1(d2, d2In0, d2In1, d2In2),
DF2(q[2], qBar2, d2, qBar1, rst),
d2In1 should be high when q is equal to 0011, which then means that d2 will be high at the same time. However you are triggering the clock to DF2 on the rising edge of qBar1, which means that at whenever qBar1 goes high, q[1] is going low, thus causing d2In1 to go low as well. So you have a race condition where the input to the flip flop is falling at the same time the clock edge is rising, which is not good!
Instead of clocking your flip flops on outputs of flip flops (which can give you nasty race conditions), you should let all your flip flops be based on just a single clock, and generate your next state based on the previous value of the flip flops.
Alternatively, here is a very simple solution (you don't always have to design the gates yourself!):
reg [3:0] q;
always #(posedge clk) begin
q <= (q == 4'd11 || rst) ? 0 : q + 1;
end
Im writing a multiplexor of 4 bits as input and 1 as output. I have tray several ways, using cases, if, etc. but I keep getting this error:
WARNING:PhysDesignRules:367 - The signal <A<2>_IBUF> is incomplete. The signal
does not drive any load pins in the design.
WARNING:Par:288 - The signal A<2>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:283 - There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
And when I program in my circuit design card (Basys), everything works fine, but the switch that is assign to A[2], doesnt work, here are my modules:
module Multi_4_1(
input [3:0] A,
input [1:0] S,
output Z
);
wire w1, w2;
Multi_2_1 a(.A(A[0]), .B(A[1]), .SEL(S[0]), .F(w1));
Multi_2_1 b(.A(A[2]), .B(A[3]), .SEL(S[1]), .F(w2));
Multi_2_1 c(.A(w1), .B(w2), .SEL(S[1]), .F(Z));
endmodule
module Multi_2_1(
input A,
input B,
input SEL,
output F
);
assign F = (~SEL&A)|(SEL&B);
endmodule
And this is where I assign the terminals to the card, but this I have tried it with another projects and it works fine
NET "A[3]" LOC ="B4"; # sw3
NET "A[2]" LOC ="K3";
NET "A[1]" LOC ="L3"; # sw1
NET "A[0]" LOC ="P11"; # sw0, el de la derecha
NET "S[0]" LOC ="G3"; # sw4
NET "S[1]" LOC ="F3"; # sw5
NET "Z" LOC ="M5"; # L0, el de la derecha
Your multiplexer has an incorrect design.
This is your truth table:
S=00 => Z=A[0]
S=01 => Z=A[1]
S=10 => Z=A[3]
S=11 => Z=A[3]
Thus A[2] can never be an output, so it is 'unloaded', and your synthesis tool is warning you of this. You probably intend for Mux b to use sel(S[0]).