While inside a module A I'm trying to use the output of a module B as the input of another module C. Essentially this is a "go" switch that is flipped in module B after certain conditions are met and then this is supposed to be the trigger for module C to activate. Is it possible to link an output and input like this?
I've been reading around and found this image particularly helpful - however, I don't quite understand the concept of nets or if they will be helpful. Would wiring the output of module B to a reg that's used as input to module C work? Thanks.
EDIT:
I'm looking for something like this (involving 3 different modules) where I'm instantiating a module B and a module C within a module A. I want to connect B's output to C's input.
Your three modules example (image), using wire outB_to_inC to connect output to input:
//A.v
module A(inA, outA);
input wire inA;
output wire outA;
wire outB_to_inC;
B B_inst(.inB(inA), .outB(outB_to_inC));
C C_inst(.inC(outB_to_inC), .outC(outA));
endmodule
/////
//B.v
module B (inB, outB);
input wire inB;
output wire outB;
//... more code here
endmodule
/////
//C.v
module C (inC, outC);
input wire inC;
output wire outC;
//... more code here
endmodule
you can make those connections
For example:
module my_moduleA (inA, outA)
input inA;
output reg outA; //If you want to assign something to out inside an always block, it has to be output reg, otherwise you will have to use assign out from an always block.
//Put your logic here
endmodule
module my_moduleB (inB, outB)
input inB;
output reg outB; //If you want to assign something to out inside an always block, it has to be output reg, otherwise you will have to use assign out from an always block.
//Put your logic here
//Instantiation of module A
my_moduleA instance( //Here is the connection made between module A and B
.inA (inB),
.outA (outB));
endmodule
This is how the connections are made, if you want to make those connections on internal signals, then you can use wire type
Related
For example, is the following code legal (with regard to the way that the modules signals are mapped), or do I have to define explicit wires to connect the modules?
module A(
output logic x;
);
module B(
input logic y;
);
A instanceOfA();
B(
.y(instanceOfA.x)
);
You can for simulation, but most synthesis tools do not accept hierarchical references.
Yes you can do that. But it's better to take a common net, which which will be driven by multiple modules.
module top ();
wire common;
A instance_a (common);
B instance_b (common);
endmodule
I have a module which holds global variables. To declare some global variables, I need to use HDF5. I am also using a library, so I also need to include a header file. So the preamble of global_variable.F90 looks like this.
module global_variables
use HDF5
#include "finclude/petscsys.h"
#include "finclude/petscvec.h"
integer(HID_T) id_file
integer(HID_T) id_plist
Vec M, C, K
...
end module
Vec is a data type defined in the header file and HID_T is a data type defined in HDF5 module.
Now, I have a file which holds subroutines for I/O. This file also uses HDF5 and the same library used in global_variables.F90. So IO.F90 looks like this.
module io
use global_varibles
contains
subroutine read_input_file( vector )
Vec vector
integer HDF5err
call H5open_f( HDF5err )
...
end subroutine
end module
Question 1: compiler returns error when compiling IO.F90, saying that Vec is undefined data type. But it does not complain about HID_T. I thought global_variables module already contains both HDF5 modules and header files, using global_variables module in IO.F90 will handle every data type declaration but it seems not. Could you please help me understand what I am understanding wrong?
Question 2: Is there a way to restrict the effect of #include to the module where it is declared?
PS. If I include #include "finclude/petscvec.h" in IO.F90, which declares Vec, then it compiles well.
The syntax
Vec vector
is completely alien to Fortran. It works only because Vec is a C pre-processor (CPP) macro defined in the header file "finclude/petscvec.h" as
#define Vec PetscFortranAddr
That means that you must include the header file in every Fortran file in which you use the above syntax with Vec. The macro cannot be inherited using the Fortran use because it is not a part of Fortran.
The PetscFortranAddr is in the end defined in "finclude/petscdef.h" as an integer with 4 or 8 bytes depending on your system.
There is probably nothing you can do except reverse engineering what it in the end the pre-processor makes to be, but I wouldn't go that way, it may be unportable.
I am in the process of writing some Verilog modules for an FPGA design. I looked around the internet to find out how I best parametrize my modules. I see two different methods occurring often. I included an example hereunder of the two different methodologies.
Which of these methods is the best way to parametrize modules?
What is the difference?
Is it vendor-dependent (Altera vs Xilinx)?
The first method:
Module definition:
module busSlave #(parameter DATA_WIDTH = 1) (
input [DATA_WIDTH-1:0] bus_data,
input bus_wr,
...
);
endmodule
Module instantiation:
module top;
//DATA_WIDTH is 32 in this instance
busSlave #(.DATA_WIDTH(32)) slave32(
.bus_data(data_0),
.bus_wr(wr_0),
...
);
//DATA_WIDTH is 64 in this instance
busSlave #(.DATA_WIDTH(64)) slave64(
.bus_data(data_1),
.bus_wr(wr_1),
...
);
endmodule
The second method:
Module definition:
module busSlave(
parameter DATA_WIDTH = 1;
input [DATA_WIDTH-1:0] bus_data,
input bus_wr,
...
);
endmodule
Module instantiation:
module top;
//DATA_WIDTH is 32 in this instance
busSlave slave32(
.bus_data(data_0),
.bus_wr(wr_0),
...
);
defparam slave32.DATA_WIDTH = 32;
//DATA_WIDTH is 64 in this instance
busSlave slave64(
.bus_data(data_1),
.bus_wr(wr_1),
...
);
defparam slave32.DATA_WIDTH = 64;
endmodule
Thanks in advance
EDIT: a few corrections in the examples
The defparam statement is scheduled for deprecation. The IEEE Std 1800-2012, Annex C (Deprecation), section "C.4.1 Defparam statements" states:
users are strongly encouraged to migrate their code to use one of the
alternate methods of parameter redefinition.
Many features of Verilog are vendor-dependent.
I have learned that I can forward commands to objects that where created in the constructor. As far as I understand it these objects exist as commands in the instance namespace.
But what do I do if the object I want to forward to has been passed to the constructor as an argument from outside instead of being created inside the constructor?
Storing it as a variable does not work, because forward works only with commands. I have thought of using interp alias to create a 'local' command that I can forward to, but I'll have to admit that the whole notion of commands vs variables still feels somewhat cumbersome to me (I'm more used to Python or C#).
For illustration see the following example:
oo::class A {
method hello {} {
puts "Hello, from [self]"
}
}
oo::class B {
constructor {some_a3} {
A create a1
A create a2
# store some_a3
variable a3
set a3 $some_a3
# this won't work because forward works on commands not variables
}
forward var1 a1
forward var2 a2
forward var3 ???
}
so that it can be used like this:
set a3 [A new]
set b [B new $a3]
$b var1 hello
$b var2 hello
$b var3 hello
PS: Should my approach be totally off course (un-TCL like) I'm willing to listen to alternative suggestions. :)
You can't forward to a variable directly; the forwarding mechanism is pretty straight-forward. But you can create the forwarding in the constructor. This is done with the oo::objdefine command, which makes per-instance changes to the object, almost as if you were changing the most-specific subclass (except it's not a class at all; it really is the instance).
oo::class B {
constructor {some_a3} {
A create a1
A create a2
##### The next line does the magic #####
oo::objdefine [self] forward var3 $some_a3
# The double-spaces are for clarity only; they separate the part that belongs
# to the call to the defining command, the forwarded method declaration, and
# what it is being forwarded to. Two spaces is as good as one in Tcl command
# invocations...
}
forward var1 a1
forward var2 a2
}
In this case, the object passed in won't be owned by the instance of B; you'll have to delete it manually. Also, you'll probably want to make sure that the command name is fully-qualified. TclOO by default returns objects as fully-qualified names, but most other Tcl commands are usually not qualified (e.g., almost all of them in both your script and mine).
I am getting an error in instantiating a module in verilog file. I am instantiating like this:
module lab3(input clk,set,reset,plus,minus,start,button,output reg [3:0]led,output reg [6:0]y);
wire [3:0] indicesgu[3:0];
reg [1:0] going;
reg alsogoing,yes;
if (going==1 && alsogoing)
begin
up_counter up_0
indicesgu ,
indices ,
alsogoing
);
end
and my up_counter module starts as:
module up_counter(input [3:0] indices_in [3:0],output [3:0]indices[3:0],output alsogoing);
reg [3:0]indices[3:0];
reg [2:0]current,setting;
when I try to compile in Xilinx, it says unexpected token up_counter.
Thanks in advance.
There are several problems with your lab3 module.
You need an endmodule at the end.
You should not instantiate up_counter inside an if. Verilog does not support conditional instances like that.
You need an opening paren after the instance name up_0.
You have (multiple) syntax errors in your code.
One of them is you need brackets () around your component port list
up_counter up_0 (indicesgu ,
indices ,
alsogoing
);
check the Verilog syntax for more info.
This will at least fix the 'unexpected token up_counter' error.