I am getting an error in instantiating a module in verilog file. I am instantiating like this:
module lab3(input clk,set,reset,plus,minus,start,button,output reg [3:0]led,output reg [6:0]y);
wire [3:0] indicesgu[3:0];
reg [1:0] going;
reg alsogoing,yes;
if (going==1 && alsogoing)
begin
up_counter up_0
indicesgu ,
indices ,
alsogoing
);
end
and my up_counter module starts as:
module up_counter(input [3:0] indices_in [3:0],output [3:0]indices[3:0],output alsogoing);
reg [3:0]indices[3:0];
reg [2:0]current,setting;
when I try to compile in Xilinx, it says unexpected token up_counter.
Thanks in advance.
There are several problems with your lab3 module.
You need an endmodule at the end.
You should not instantiate up_counter inside an if. Verilog does not support conditional instances like that.
You need an opening paren after the instance name up_0.
You have (multiple) syntax errors in your code.
One of them is you need brackets () around your component port list
up_counter up_0 (indicesgu ,
indices ,
alsogoing
);
check the Verilog syntax for more info.
This will at least fix the 'unexpected token up_counter' error.
Related
I want to write a testbench for a module that instantiates several components but has no significant outputs. To test the correctness I'd have to access variables of components of the uut. At least being able to access variables of the uut would be helpful.
I would imagine that to work a little like this:
uut: top_module port map(
i_clk => clk,
i_reset => reset
);
testbench: process
begin
wait for CLK_PERIOD;
report STD_LOGIC'image(top_module.flag) severity note;
end process;
Of course I can write the testbench in a way that it replaces the top module but then I wouldn't be able to test that model. Expanding the output of the top module/uut is also not really an option.
With VHDL 2008 you can use the new external names syntax:
alias int1 << signal .tb_top.u_ioc.int1 : std_logic >>;
With an earlier VHDL standard you have to use vendor-specific tools, e.g. signal_spy for Questa/ModelSim.
Another method would be to write your testbench at a lower level, e.g. connect your sub-components inside the testbench instead of testing the highest-level entity.
I am trying to call one of the 2 modules (fifo_test_1 or fifo_test_2) depending on the value of bit data[0] in the following Verilog code.
module VC_selector(data);
input [10:0] data;
always # (data[0])
begin
if(~data[0])
begin
fifo_test_1 t1(.buf_in(data));
end
else if (data[0])
begin
fifo_test_2 t2 (.buf_in(data));
end
end
endmodule
fifo_test_1 and fifo_test_2 modules are working fine. But the above code gives these errors:
** Error: C:/Users/Swayam/Documents/VC_selector.v(8): Undefined variable: fifo_test_1.
** Error: C:/Users/Swayam/Documents/VC_selector.v(8): near "t1": syntax error, unexpected IDENTIFIER
** Error: C:/Users/Swayam/Documents/VC_selector.v(12): Undefined variable: fifo_test_2.
** Error: C:/Users/Swayam/Documents/VC_selector.v(12): near "t2": syntax error, unexpected IDENTIFIER
Please help me debug the code.
You cannot change the modules included while the hardware is running. The modules must be a constant during execution. For that reason, you can't include a module definition inside an always statement.
One thing you could do is move the two modules outside the always block and use some logic to switch between their outputs. Because neither of the fifo modules have outputs that would be rather difficult to do in this particular case, but it is possible in the general case.
assign my_switched_output = data[0] ? module_1_output : module_2_output;
The ternary operator (used here) allows you to do this switching that it appears you are attempting to do.
Another thing to make sure you have done is to include both the module file you are trying to simulate/synthesize AND all of the submodule verilog files you need in the command. How to include all of these files based on the simulator.
I am in the process of writing some Verilog modules for an FPGA design. I looked around the internet to find out how I best parametrize my modules. I see two different methods occurring often. I included an example hereunder of the two different methodologies.
Which of these methods is the best way to parametrize modules?
What is the difference?
Is it vendor-dependent (Altera vs Xilinx)?
The first method:
Module definition:
module busSlave #(parameter DATA_WIDTH = 1) (
input [DATA_WIDTH-1:0] bus_data,
input bus_wr,
...
);
endmodule
Module instantiation:
module top;
//DATA_WIDTH is 32 in this instance
busSlave #(.DATA_WIDTH(32)) slave32(
.bus_data(data_0),
.bus_wr(wr_0),
...
);
//DATA_WIDTH is 64 in this instance
busSlave #(.DATA_WIDTH(64)) slave64(
.bus_data(data_1),
.bus_wr(wr_1),
...
);
endmodule
The second method:
Module definition:
module busSlave(
parameter DATA_WIDTH = 1;
input [DATA_WIDTH-1:0] bus_data,
input bus_wr,
...
);
endmodule
Module instantiation:
module top;
//DATA_WIDTH is 32 in this instance
busSlave slave32(
.bus_data(data_0),
.bus_wr(wr_0),
...
);
defparam slave32.DATA_WIDTH = 32;
//DATA_WIDTH is 64 in this instance
busSlave slave64(
.bus_data(data_1),
.bus_wr(wr_1),
...
);
defparam slave32.DATA_WIDTH = 64;
endmodule
Thanks in advance
EDIT: a few corrections in the examples
The defparam statement is scheduled for deprecation. The IEEE Std 1800-2012, Annex C (Deprecation), section "C.4.1 Defparam statements" states:
users are strongly encouraged to migrate their code to use one of the
alternate methods of parameter redefinition.
Many features of Verilog are vendor-dependent.
While inside a module A I'm trying to use the output of a module B as the input of another module C. Essentially this is a "go" switch that is flipped in module B after certain conditions are met and then this is supposed to be the trigger for module C to activate. Is it possible to link an output and input like this?
I've been reading around and found this image particularly helpful - however, I don't quite understand the concept of nets or if they will be helpful. Would wiring the output of module B to a reg that's used as input to module C work? Thanks.
EDIT:
I'm looking for something like this (involving 3 different modules) where I'm instantiating a module B and a module C within a module A. I want to connect B's output to C's input.
Your three modules example (image), using wire outB_to_inC to connect output to input:
//A.v
module A(inA, outA);
input wire inA;
output wire outA;
wire outB_to_inC;
B B_inst(.inB(inA), .outB(outB_to_inC));
C C_inst(.inC(outB_to_inC), .outC(outA));
endmodule
/////
//B.v
module B (inB, outB);
input wire inB;
output wire outB;
//... more code here
endmodule
/////
//C.v
module C (inC, outC);
input wire inC;
output wire outC;
//... more code here
endmodule
you can make those connections
For example:
module my_moduleA (inA, outA)
input inA;
output reg outA; //If you want to assign something to out inside an always block, it has to be output reg, otherwise you will have to use assign out from an always block.
//Put your logic here
endmodule
module my_moduleB (inB, outB)
input inB;
output reg outB; //If you want to assign something to out inside an always block, it has to be output reg, otherwise you will have to use assign out from an always block.
//Put your logic here
//Instantiation of module A
my_moduleA instance( //Here is the connection made between module A and B
.inA (inB),
.outA (outB));
endmodule
This is how the connections are made, if you want to make those connections on internal signals, then you can use wire type
i have a module 'gvars' defined for my global variable declarations. when i define
integer :: nthreads, max_threads, tid, omp_get_max_threads, omp_get_num_threads, omp_get_thread_num inside of my gvars module, the call maxthreads = omp_get_max_threads() in my main routine gives me the following error upon compilation:
maxthreads = omp_get_max_threads()
1
Error: Unclassifiable statement at (1)
but when i include the integer :: definitions above inside my main routine, it compiles just fine and gives me the desired results. if i even go as far as to define nthreads = -1 inside my gvars module, i am able to print out the correct value in my main routine so i know it is being included and defined correctly, it's just that for some reason i cannot have it as a return value from openmp functions.
why would this be?
is there any other way to keep these values as global variables and still define them in my main routine instead of a module?
if it matters, i am using gfortran to compile
The problem is not with the declaration of maxthreads, but with the declaration, on the same line, of omp_get_max_threads. As haraldkl showed, you need to use omp_lib instead, to automatically get access to the declarations of these functions.
(If for some reason you really don't want to do it that way, you can also add the statement external :: omp_get_max_threads, ... to the module.)
Not really an answer, but I do not know how else to put the code in here. Sorry...
module gvars
integer :: maxthreads
end module gvars
program test
use gvars
use omp_lib
implicit none
maxthreads = omp_get_max_threads()
end program test
compiled with:
gfortran -fopenmp test.f90
Where gfotran -v gives:
gcc version 4.4.5 (GCC)