How can I read or write verilog reg (variable) in NIOS CPU?
What should I do?
I use DE0 NANO, cyclone IV and NIOS 2.
Related
We encounter FLEXSPI erase and write issue. We use the following commands to test FLEXSPI read, write, and erase.
mtd_debug erase /dev/mtd2 0x0000000 0x10000
dd if=/dev/zero of=data.hex count=1 bs=65536
mtd_debug write /dev/mtd2 0x0000000 0x10000 data.hex
mtd_debug read /dev/mtd2 0x0000000 0x10000 dump
The contents of data.hex and dump files should be same. But unfortunately the contents of these two files are not identical.
spi-nxp-fspi.c is FLEXSPI driver source file.
I have fixed this issue by disabling erasing and writing protection from NOR flash register.
I am attached to a running proces using dbx on AIX. There is a bug in the program, the offset in the opcode below is 0x9b8, but should be 0xbe8:
(dbx) listi 0x100001b14
0x100001b14 (..........+0x34) e88109b8 ld r4,0x9b8(r1)
I am able to fix that using the command below:
(dbx) assign 0x100001b14 = 0xe8810be8
but that affects only the running process and its memory. How can I change the on disk binary? I am not able to locate the pattern e88109b8 in the binary file,
otherwise I would use e.g. dd utility to patch it.
Best regards,
Pavel Filipensky
i know that every instruction has opcodes.
i could find opcodes for mov , sub instructions.
but what is the opcode for variables and it's types.
we use assembler directives to define a variable and constant?
how they are represented in x86 opcodes?
nasm assembler x86: segment .bss
largest resb 2 ; reserves two bytes for largest
segment .data
number1 DW 12345 ; defines a constant number1
i tried online this https://defuse.ca/online-x86-assembler.htm#disassembly assembly to opcode conveter. but when i used nasm code to define a variable it shows error!
There's no opcode for variables. There are even no variables in machine code.
There is CPU and memory. Memory contains some values (bytes).
The CPU has cs:ip instruction pointer, pointing to memory address, where is the next instruction to execute, so it will read byte(s) from that address, and interpret them as opcode, and execute it as an instruction.
Whether you have in memory stored data or machine code doesn't matter, both are byte values.
What makes part of memory "data" or "variable" is the logical interpretation created by the running code, it's the code which does use certain part of memory only as "data/variables" and other part of memory as "code" (or eventually as both at the same time, like in this DOS 51B long COM code drawing Greece flag on screen, where the XLAT instruction is using the code opcodes also as source data for blue/white strips configuration).
Whether you write in your source:
x:
add al,al
or
x:
db 0x00, 0xC0
Doesn't matter, the resulting machine code is identical (in both cases the CPU will execute add al,al when pointed to that memory to be executed as instruction, and mov ax,[x] will set ax to 0xC000 in both cases, when used as "variable".
You may want to check listing file from the assembler (-l <listing_file_name> command line option for nasm) to see yourself there's no way to tell which bytes are code and which are data.
Assembler directives like segment, resb, or dw are not instructions and do not correspond to opcodes. That's why they are directives instead of instructions. Roughly speaking, there are two kinds of directives:
one kind of directive configures the assembler. For example, the segment directive configures the assembler to continue assembly in the section you provided.
another kind of directive emits data. For example, the dw directive emits the given datum into the object file. This can be used to place arbitrary data into memory for use with your program.
It is good design practice to not only verify Verilog designs with regular pre-synthesis (behavioral) simulation, but also using post-synthesis simulation. This is practically mandatory when debugging mismatches between simulation and hardware. How can this be achieved with the open source IceStorm flow for iCE40 FPGAs?
See https://github.com/cliffordwolf/icestorm/tree/master/examples/icestick for an example. The "rs232demo" project comes with a test bench and the Makefile contains rules for pre- and post-synthesis simulation:
make rs232demo_tb.vcd # pre-synthesis simulation
make rs232demo_syntb.vcd # post-synthesis simulation
Use a VCD viewer like gtkwave to view the VCD files generated by this two commands.
In order to run post-synthesis simulation one must first convert the BLIF netlist (synthesis output) to a Verilog netlist: yosys -p 'read_blif -wideports example.blif; write_verilog example_syn.v'
This netlist will instantiate iCE40 device primitives. Yosys comes with simulation models for those primitives. Run the command yosys-config --datdir/ice40/cells_sim.v to print the full path name of that simulation library. Use this Verilog file when compiling your simulation.
Edit: Two additional FAQs regarding post-synthesis simulation:
(1) The clock should not have a clock edge at timestamp 0 as this can result in a race condition between clocked register updates and register initialization. I.e. the following test bench code for generating the clock is problematic:
reg clk = 1;
always #5 clk = ~clk;
Instead you should use something like the following, that leaves the clock signal undefined for an initial period:
reg clk;
always #5 clk = (clk === 1'b0);
(2) Some signals (or individual bits of a vector) can be optimized away during synthesis. This bits may be set to a constant value (usually x) or left floating by the tool. This can be confusing when trying to inspect post-synthesis simulation results. Set the keep attribute on nets that you want the tool to preserve:
(* keep *) reg [31:0] foobar;
I want to execute one shell command (gcore $pid) at the end of pin tool.
In order to complete this goal, I try to modify the itrace pin tool and do one simple shell command first. I add one statement system("ls > /tmp/test") at the starting of Fini function. Then compile the pin tool again.
Run the pin tool - itrace:
../../../pin -t obj-intel64/itrace.so -- /bin/ls
But there does not exist file - "/tmp/test".
the libc function system() is not yet implemented in PinCRT.
Please use popen() (which is implemented) instead.
source.